Re: [PATCH] iommu: riscv: Split 8-byte accesses on 32 bit I/O bus platform

From: David Laight <david.laight.linux@gmail.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: Xu Lu <luxu.kernel@bytedance.com>,
	tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org,
	alex@ghiti.fr, lihangjing@bytedance.com, xieyongji@bytedance.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	iommu@lists.linux.dev
Subject: Re: [PATCH] iommu: riscv: Split 8-byte accesses on 32 bit I/O bus platform
Date: Wed, 2 Apr 2025 14:00:34 +0100	[thread overview]
Message-ID: <20250402140034.0fc4cbac@pumpkin> (raw)
In-Reply-To: <8cfe938f-5eff-483e-95a1-c4029993e287@arm.com>

On Wed, 2 Apr 2025 12:28:54 +0100
Robin Murphy <robin.murphy@arm.com> wrote:

...
> It is not, in general, safe to do a split write to a running counter 
> either way - low-high vs. high-low just moves the problem around, 
> changing *which* combinations of values are problematic and capable of 
> overflowing into each other between the writes. If the PMU driver can't 
> write counters atomically, it will need to ensure that it only ever 
> write them while stopped (at which point the order surely shouldn't 
> matter). Conversely, though, reading from running counters is a bit more 
> reasonable, but it needs more than just hi_lo_readq to guarantee it's 
> not got a torn result.

Or have hardware that latches a value waiting for the following cycle.
That could be done in the bus interface logic.
In which case the cycle better come from the same cpu, not another
cpu accessing an entirely different register.
That requires a global lock for the device.

	David

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