From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 798AAC36010 for ; Mon, 7 Apr 2025 10:50:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9vGgAi9tZT4JqiGqLHCM/GoSC0h3lhcFYeSmi84RDdw=; b=WPM7E9ocfjyK+H TqCZ7pR7Bu1UoKb+Gei1i77v425ekMOiygZ51dMjPmZR7Xui1GLr2OkhdK9l8bzd1ZjSAH0/T606F yX5VjGkHyeqNm42qrrKKcD/9HTeU6ztU3e/AiJEczY/fiEG5t7mMqzQqWqk27HCvzKE7TKLv6jMqk S951c57sLLWLIZEK5v/XtlraglUfWAhRzw2tP5TUVQnKHPiaXPu80eRTwrNz+urj/qXJUxNFrzPtD a/cDhwdspg3rMwCWnJrZqA2YPDfpZFzwSCG8lXZuLUyPD5e0eU3LpXdYl4PuBc8Bumnx05Hs+fJWV oc7Y91w8twHy1sgG/mpw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.1 #2 (Red Hat Linux)) id 1u1k3q-0000000HQ5Y-2sa4; Mon, 07 Apr 2025 10:50:38 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.98.1 #2 (Red Hat Linux)) id 1u1k3k-0000000HQ0o-3b67 for linux-riscv@lists.infradead.org; Mon, 07 Apr 2025 10:50:36 +0000 Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 537Anj3v001585 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 7 Apr 2025 18:49:45 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 7 Apr 2025 18:49:45 +0800 From: Ben Zong-You Xie To: , , CC: , , , , , , , , , , , "Ben Zong-You Xie" Subject: [PATCH 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Date: Mon, 7 Apr 2025 18:49:32 +0800 Message-ID: <20250407104937.315783-5-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250407104937.315783-1-ben717@andestech.com> References: <20250407104937.315783-1-ben717@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 537Anj3v001585 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250407_035033_216501_9CB993BA X-CRM114-Status: GOOD ( 13.22 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the DT binding documentation for Andes machine-level software interrupt controller. In the Andes platform such as QiLai SoC, the PLIC module is instantiated a second time with all interrupt sources tied to zero as the software interrupt controller (PLICSW). PLICSW can generate machine-level software interrupts through programming its registers. Signed-off-by: Ben Zong-You Xie --- .../andestech,plicsw.yaml | 48 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml new file mode 100644 index 000000000000..5432fcfd95ed --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes machine-level software interrupt controller + +description: + In the Andes platform such as QiLai SoC, the PLIC module is instantiated a + second time with all interrupt sources tied to zero as the software interrupt + controller (PLIC_SW). PLIC_SW can generate machine-level software interrupts + through programming its registers. + +maintainers: + - Ben Zong-You Xie + +properties: + compatible: + items: + - enum: + - andestech,qilai-plicsw + - const: andestech,plicsw + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 15872 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@400000 { + compatible = "andestech,qilai-plicsw", "andestech,plicsw"; + reg = <0x400000 0x400000>; + interrupts-extended = <&cpu0intc 3>, + <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index a0ccac1cca29..645d7137cb07 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20728,6 +20728,7 @@ F: include/linux/irqchip/riscv-imsic.h RISC-V ANDES SoC Support M: Ben Zong-You Xie S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml F: Documentation/devicetree/bindings/riscv/andes.yaml RISC-V ARCHITECTURE -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv