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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Apr 07, 2025 at 06:49:32PM +0800, Ben Zong-You Xie wrote: > Add the DT binding documentation for Andes machine-level software > interrupt controller. > > In the Andes platform such as QiLai SoC, the PLIC module is instantiated a > second time with all interrupt sources tied to zero as the software > interrupt controller (PLICSW). PLICSW can generate machine-level software > interrupts through programming its registers. > > Signed-off-by: Ben Zong-You Xie > --- > .../andestech,plicsw.yaml | 48 +++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 49 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml > new file mode 100644 > index 000000000000..5432fcfd95ed > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Andes machine-level software interrupt controller > + > +description: > + In the Andes platform such as QiLai SoC, the PLIC module is instantiated a > + second time with all interrupt sources tied to zero as the software interrupt > + controller (PLIC_SW). PLIC_SW can generate machine-level software interrupts > + through programming its registers. > + > +maintainers: > + - Ben Zong-You Xie > + > +properties: > + compatible: > + items: > + - enum: > + - andestech,qilai-plicsw > + - const: andestech,plicsw Drop the fallback. If you have another implementation that's compatible, then andestech,qilai-plicsw will be the fallback. > + > + reg: > + maxItems: 1 > + > + interrupts-extended: > + minItems: 1 > + maxItems: 15872 > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts-extended > + > +examples: > + - | > + interrupt-controller@400000 { > + compatible = "andestech,qilai-plicsw", "andestech,plicsw"; > + reg = <0x400000 0x400000>; > + interrupts-extended = <&cpu0intc 3>, > + <&cpu1intc 3>, > + <&cpu2intc 3>, > + <&cpu3intc 3>; > + }; > diff --git a/MAINTAINERS b/MAINTAINERS > index a0ccac1cca29..645d7137cb07 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -20728,6 +20728,7 @@ F: include/linux/irqchip/riscv-imsic.h > RISC-V ANDES SoC Support > M: Ben Zong-You Xie > S: Maintained > +F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml > F: Documentation/devicetree/bindings/riscv/andes.yaml > > RISC-V ARCHITECTURE > -- > 2.34.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv