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Fri, 25 Apr 2025 06:33:55 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::f716]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca4e50sm2467062f8f.30.2025.04.25.06.33.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 06:33:55 -0700 (PDT) Date: Fri, 25 Apr 2025 15:33:54 +0200 From: Andrew Jones To: Atish Patra Cc: Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/3] KVM: riscv: selftests: Decode stval to identify exact exception type Message-ID: <20250425-f458b9801a83cc35bda55c74@orel> References: <20250324-kvm_selftest_improve-v1-0-583620219d4f@rivosinc.com> <20250324-kvm_selftest_improve-v1-2-583620219d4f@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250324-kvm_selftest_improve-v1-2-583620219d4f@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250425_063357_579118_F01CCE1B X-CRM114-Status: GOOD ( 20.68 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Mar 24, 2025 at 05:40:30PM -0700, Atish Patra wrote: > Currently, the sbi_pmu_test continues if the exception type is illegal > instruction because access to hpmcounter will generate that. However, we > may get illegal for other reasons as well which should result in test > assertion. > > Use the stval to decode the exact type of instructions and which csrs are > being accessed if it is csr access instructions. Assert in all cases > except if it is a csr access instructions that access valid PMU related > registers. > > Signed-off-by: Atish Patra > --- > tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 32 ++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c > index 03406de4989d..11bde69b5238 100644 > --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c > +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c > @@ -128,11 +128,43 @@ static void stop_counter(unsigned long counter, unsigned long stop_flags) > "Unable to stop counter %ld error %ld\n", counter, ret.error); > } > > +#define INSN_OPCODE_MASK 0x007c > +#define INSN_OPCODE_SHIFT 2 > +#define INSN_OPCODE_SYSTEM 28 > + > +#define INSN_MASK_FUNCT3 0x7000 > +#define INSN_SHIFT_FUNCT3 12 > + > +#define INSN_CSR_MASK 0xfff00000 > +#define INSN_CSR_SHIFT 20 > + > +#define GET_RM(insn) (((insn) & INSN_MASK_FUNCT3) >> INSN_SHIFT_FUNCT3) > +#define GET_CSR_NUM(insn) (((insn) & INSN_CSR_MASK) >> INSN_CSR_SHIFT) It'd be good to put these macros in include/riscv/processor.h or some new include/riscv/ header to be shared with other tests that may want to decode stval. Thanks, drew > + > static void guest_illegal_exception_handler(struct ex_regs *regs) > { > + unsigned long insn; > + int opcode, csr_num, funct3; > + > __GUEST_ASSERT(regs->cause == EXC_INST_ILLEGAL, > "Unexpected exception handler %lx\n", regs->cause); > > + insn = regs->stval; > + opcode = (insn & INSN_OPCODE_MASK) >> INSN_OPCODE_SHIFT; > + __GUEST_ASSERT(opcode == INSN_OPCODE_SYSTEM, > + "Unexpected instruction with opcode 0x%x insn 0x%lx\n", opcode, insn); > + > + csr_num = GET_CSR_NUM(insn); > + funct3 = GET_RM(insn); > + /* Validate if it is a CSR read/write operation */ > + __GUEST_ASSERT(funct3 <= 7 && (funct3 != 0 || funct3 != 4), > + "Unexpected system opcode with funct3 0x%x csr_num 0x%x\n", > + funct3, csr_num); > + > + /* Validate if it is a HPMCOUNTER CSR operation */ > + __GUEST_ASSERT(csr_num == CSR_CYCLE || csr_num <= CSR_HPMCOUNTER31, > + "Unexpected csr_num 0x%x\n", csr_num); > + > illegal_handler_invoked = true; > /* skip the trapping instruction */ > regs->epc += 4; > > -- > 2.43.0 > > > -- > kvm-riscv mailing list > kvm-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/kvm-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv