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Sat, 03 May 2025 17:44:42 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with UTF8SMTPSA id 6a1803df08f44-6f50f3b05efsm38597456d6.23.2025.05.03.17.44.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 May 2025 17:44:42 -0700 (PDT) From: Inochi Amaoto To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Niklas Cassel , Johan Hovold , Shradha Todi , Thippeswamy Havalige , Shashank Babu Chinta Venkata Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Yixun Lan , Longbin Li Subject: [PATCH v3 0/2] riscv: sophgo Add PCIe support to Sophgo SG2044 SoC Date: Sun, 4 May 2025 08:44:17 +0800 Message-ID: <20250504004420.202685-1-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250503_174444_527462_E8F8E1AB X-CRM114-Status: GOOD ( 11.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Sophgo's SG2044 SoC uses Synopsys Designware PCIe core to implement RC mode. For legacy interrupt, the PCIe controller on SG2044 implement its own legacy interrupt controller. For MSI/MSI-X, it use an external interrupt controller to handle. The external MSI interrupt controller patch can be found on [1]. As SG2044 needs a mirror change to support the way to send MSI message and different irq number. [1] https://lore.kernel.org/all/20250413224922.69719-1-inochiama@gmail.com Changed from v2: - https://lore.kernel.org/all/20250304071239.352486-1-inochiama@gmail.com 1. patch 1: remove "|+" for description 2. patch 1: apply Rob's tag 3. patch 2: remove empty irq_eoi and use handle_level_irq as the right irq handle function. Changed from v1: - https://lore.kernel.org/all/20250221013758.370936-1-inochiama@gmail.com 1. patch 1: remove dma-coherent property 2. patch 2: remove unused reset 3. patch 2: fix Kconfig menu title and reorder the entry 4. patch 2: use FIELD_GET/FIELD_PREP to simplify the code. 5. patch 2: rename the irq handle function to match the irq_chip name Inochi Amaoto (2): dt-bindings: pci: Add Sophgo SG2044 PCIe host PCI: sophgo-dwc: Add Sophgo SG2044 PCIe driver .../bindings/pci/sophgo,sg2044-pcie.yaml | 122 +++++++++ drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-dw-sophgo.c | 258 ++++++++++++++++++ 4 files changed, 391 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-dw-sophgo.c -- 2.49.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv