From: Conor Dooley <conor@kernel.org>
To: linux-renesas-soc@vger.kernel.org
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
Ben Zong-You Xie <ben717@andestech.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: [PATCH v1 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible
Date: Fri, 9 May 2025 16:37:59 +0100 [thread overview]
Message-ID: <20250509-mantra-trickery-56f699596346@spud> (raw)
In-Reply-To: <20250509-sapling-exhale-72815a023ac1@spud>
From: Conor Dooley <conor.dooley@microchip.com>
When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.
Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index e0ddf8f602c79..66c6fe0cd162f 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -143,7 +143,7 @@ plic: interrupt-controller@12c00000 {
};
l2cache: cache-controller@13400000 {
- compatible = "andestech,ax45mp-cache", "cache";
+ compatible = "renesas,r9a07g043f-cache", "andestech,ax45mp-cache", "cache";
reg = <0x0 0x13400000 0x0 0x100000>;
interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
cache-size = <0x40000>;
--
2.45.2
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next prev parent reply other threads:[~2025-05-09 17:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-09 15:37 [PATCH v1 0/2] Add specific RZ/Five cache compatible Conor Dooley
2025-05-09 15:37 ` [PATCH v1 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp Conor Dooley
2025-05-12 9:01 ` Geert Uytterhoeven
2025-05-12 9:59 ` Conor Dooley
2025-05-12 10:05 ` Lad, Prabhakar
2025-05-12 11:05 ` Geert Uytterhoeven
2025-05-12 11:53 ` Conor Dooley
2025-05-12 12:01 ` Lad, Prabhakar
2025-05-09 15:37 ` Conor Dooley [this message]
2025-05-12 8:00 ` [PATCH v1 0/2] Add specific RZ/Five cache compatible Geert Uytterhoeven
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