From: Conor Dooley <conor@kernel.org>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: linux-renesas-soc@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>,
Ben Zong-You Xie <ben717@andestech.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Magnus Damm <magnus.damm@gmail.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible
Date: Mon, 12 May 2025 16:54:04 +0100 [thread overview]
Message-ID: <20250512-neglector-scope-65dd0e24db8f@spud> (raw)
In-Reply-To: <CAMuHMdVwBqC3jHgwLJkLcNZo8W0Aw9ZfoXL1tRaL7B2EpKuWvg@mail.gmail.com>
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On Mon, May 12, 2025 at 03:57:41PM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Mon, 12 May 2025 at 15:48, Conor Dooley <conor@kernel.org> wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > When the binding was originally written, it was assumed that all
> > ax45mp-caches had the same properties etc. This has turned out to be
> > incorrect, as the QiLai SoC has a different number of cache-sets.
> >
> > Add a specific compatible for the RZ/Five for property enforcement and
> > in case there turns out to be additional differences between these
> > implementations of the cache controller.
> >
> > Acked-by: Ben Zong-You Xie <ben717@andestech.com>
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks for the update!
>
> > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -143,7 +143,8 @@ plic: interrupt-controller@12c00000 {
> > };
> >
> > l2cache: cache-controller@13400000 {
> > - compatible = "andestech,ax45mp-cache", "cache";
> > + compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
> > + "cache";
> > reg = <0x0 0x13400000 0x0 0x100000>;
> > interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
> > cache-size = <0x40000>;
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-devel for v6.16 if there are no objections.
I'll grab the binding then on that basis. :+1:
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next prev parent reply other threads:[~2025-05-12 16:20 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-12 13:48 [PATCH v2 0/2] Add specific RZ/Five cache compatible Conor Dooley
2025-05-12 13:48 ` [PATCH v2 1/2] dt-bindings: cache: add specific RZ/Five compatible to ax45mp Conor Dooley
2025-05-12 13:56 ` Geert Uytterhoeven
2025-05-13 7:42 ` Lad, Prabhakar
2025-05-12 13:48 ` [PATCH v2 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible Conor Dooley
2025-05-12 13:57 ` Geert Uytterhoeven
2025-05-12 15:54 ` Conor Dooley [this message]
2025-05-13 7:42 ` Lad, Prabhakar
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