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From: Qingfang Deng <dqfext@gmail.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Himanshu Chauhan <hchauhan@ventanamicro.com>,
	Charlie Jenkins <charlie@rivosinc.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu
Subject: Re: [RFC PATCH 2/2] riscv: Introduce support for hardware break/watchpoints
Date: Mon, 12 May 2025 11:31:17 +0800	[thread overview]
Message-ID: <20250512033118.1071577-1-dqfext@gmail.com> (raw)
In-Reply-To: <20240222125059.13331-3-hchauhan@ventanamicro.com>

Hi, Himanshu and Charlie,

> +static int arch_smp_setup_sbi_shmem(unsigned int cpu)
> +{
> +	struct sbi_dbtr_shmem_entry *dbtr_shmem;
> +	unsigned long shmem_pa;
> +	struct sbiret ret;
> +	int rc;
> +
> +	dbtr_shmem = per_cpu_ptr(sbi_dbtr_shmem, cpu);
> +	if (!dbtr_shmem) {
> +		pr_err("Invalid per-cpu shared memory for debug triggers\n");
> +		return -ENODEV;
> +	}
> +
> +	shmem_pa = __pa(dbtr_shmem);
> +
> +	ret = sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_SETUP_SHMEM,
> +			(!MEM_LO(shmem_pa) ? 0xFFFFFFFFUL : MEM_LO(shmem_pa)),
> +			(!MEM_HI(shmem_pa) ? 0xFFFFFFFFUL : MEM_HI(shmem_pa)),
> +			 0, 0, 0, 0);
> +
> +	if (ret.error) {
> +		switch(ret.error) {
> +		case SBI_ERR_DENIED:
> +			pr_warn("%s: Access denied for shared memory at %lx\n",
> +				__func__, shmem_pa);
> +			rc = -EPERM;
> +			break;
> +
> +		case SBI_ERR_INVALID_PARAM:
> +		case SBI_ERR_INVALID_ADDRESS:
> +			pr_warn("%s: Invalid address parameter (%lu)\n",
> +				__func__, ret.error);
> +			rc = -EINVAL;
> +			break;
> +
> +		case SBI_ERR_ALREADY_AVAILABLE:
> +			pr_warn("%s: Shared memory is already set\n",
> +				__func__);
> +			rc = -EADDRINUSE;
> +			break;
> +
> +		case SBI_ERR_FAILURE:
> +			pr_err("%s: Internal sdtrig state error\n",
> +			       __func__);
> +			rc = -ENXIO;
> +			break;
> +
> +		default:
> +			pr_warn("%s: Unknown error %lu\n", __func__, ret.error);
> +			rc = -ENXIO;
> +			break;
> +		}
> +	}
> +
> +	pr_warn("CPU %d: HW Breakpoint shared memory registered.\n", cpu);

This is printed unconditionally, even if there is an error above.

> +
> +	return rc;

If ret.error is 0, rc is uninitialized here, which may explain the error
that Charlie came across.

Regards,

-- Qingfang

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  parent reply	other threads:[~2025-05-12  3:31 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-22 12:50 [RFC PATCH 0/2] Introduce support for hardware break/watchpoints Himanshu Chauhan
2024-02-22 12:50 ` [RFC PATCH 1/2] riscv: Add SBI debug trigger extension and function ids Himanshu Chauhan
2024-02-22 12:50 ` [RFC PATCH 2/2] riscv: Introduce support for hardware break/watchpoints Himanshu Chauhan
2025-05-06  2:00   ` Charlie Jenkins
2025-05-07 11:28     ` Himanshu Chauhan
2025-05-07 21:32       ` Charlie Jenkins
2025-05-08 11:54         ` Himanshu Chauhan
2025-05-08 19:34           ` Charlie Jenkins
2025-05-12  3:31   ` Qingfang Deng [this message]
2025-05-12  5:15     ` Himanshu Chauhan

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