From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 834FBC3ABCB for ; Mon, 12 May 2025 22:58:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=L98k52Du2e5Rx67cFbeMmQz0pvI5hKWb4pt6vW2H86w=; b=sAqD7HrtY7invw IDojbcqHmiZyFLILZvIvXUar+NFPvTwghXTmN4mAb4TgkXMWHV27iCrAoGb/MoKRvL3AvDbq+9fyY FlV+nTZiD3k8bz++xrz4k7UNfRVWGf3zDZqt47W2NqnMDOLY77zmce3sotpfJsh5S+PFRLPviw7qF ViU1Lq14X86OY7pEZ9sKivoBHHC1OQigrjrLy2VGcaZcTmQQB+af+CS1eO/LZUfojYx/avddetRUD MwW+q9ZKgIxGR2JE9XvTYRQKt7P2EV6b/C09T6M2mD5XcibyMXa3b7Km1mi8LardEiLB5VMjc12AK sWVzvVqAgj/0ppVTgXKg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uEc6h-0000000At2c-0arP; Mon, 12 May 2025 22:58:47 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uEc4b-0000000Aspq-2SG3; Mon, 12 May 2025 22:56:39 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 022FC150C; Mon, 12 May 2025 15:56:24 -0700 (PDT) Received: from minigeek.lan (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 666963F673; Mon, 12 May 2025 15:56:32 -0700 (PDT) Date: Mon, 12 May 2025 23:56:19 +0100 From: Andre Przywara To: Aleksandr Shubin Cc: linux-kernel@vger.kernel.org, Conor Dooley , Uwe =?UTF-8?B?S2xlaW5lLUvDtm5pZw==?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Philipp Zabel , Cheo Fusi , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: Re: [PATCH v12 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller Message-ID: <20250512235619.30cff739@minigeek.lan> In-Reply-To: <20250427142500.151925-2-privatesub2@gmail.com> References: <20250427142500.151925-1-privatesub2@gmail.com> <20250427142500.151925-2-privatesub2@gmail.com> Organization: Arm Ltd. X-Mailer: Claws Mail 4.2.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250512_155637_816217_39DCB739 X-CRM114-Status: GOOD ( 23.43 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, 27 Apr 2025 17:24:53 +0300 Aleksandr Shubin wrote: Hi, > Allwinner's D1, T113-S3 and R329 SoCs have a new pwm > controller witch is different from the previous pwm-sun4i. > > The D1 and T113 are identical in terms of peripherals, > they differ only in the architecture of the CPU core, and > even share the majority of their DT. Because of that, > using the same compatible makes sense. > The R329 is a different SoC though, and should have > a different compatible string added, especially as there > is a difference in the number of channels. > > D1 and T113s SoCs have one PWM controller with 8 channels. > R329 SoC has two PWM controllers in both power domains, one of > them has 9 channels (CPUX one) and the other has 6 (CPUS one). > > Add a device tree binding for them. > > Reviewed-by: Conor Dooley > Signed-off-by: Aleksandr Shubin > --- > .../bindings/pwm/allwinner,sun20i-pwm.yaml | 84 +++++++++++++++++++ > 1 file changed, 84 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > new file mode 100644 > index 000000000000..4b25e94a8e46 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > @@ -0,0 +1,84 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner D1, T113-S3 and R329 PWM > + > +maintainers: > + - Aleksandr Shubin > + - Brandon Cheo Fusi > + > +properties: > + compatible: > + oneOf: > + - const: allwinner,sun20i-d1-pwm > + - items: > + - const: allwinner,sun50i-r329-pwm > + - const: allwinner,sun20i-d1-pwm > + > + reg: > + maxItems: 1 > + > + "#pwm-cells": > + const: 3 > + > + clocks: > + items: > + - description: Bus clock > + - description: 24 MHz oscillator > + - description: APB clock > + > + clock-names: > + items: > + - const: bus > + - const: hosc > + - const: apb > + > + resets: > + maxItems: 1 > + > + allwinner,npwms: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: The number of PWM channels configured for this instance > + enum: [6, 8, 9] Do we really need to be so restrictive here? The IP has an "architectural" limit of 16 channels (due to the MMIO register layout and status/control bits usage in some registers), so can't we just leave this value to be anything between 1 and 16 here? If people configure this wrongly, it's their fault, I'd say? Without confining this further based on the respective compatible strings this enum is less useful anyway, I think. The Allwinner A523 uses the same IP, and supports all 16 channels, the V853 implements 12, that's what I quickly found already, and there might be more examples in the future, so I'd rather open this up. > + > +allOf: > + - $ref: pwm.yaml# > + > + - if: > + properties: > + compatible: > + contains: > + const: allwinner,sun50i-r329-pwm > + > + then: > + required: > + - allwinner,npwms Can't we just simplify this by always requiring this property? As mentioned, there will be more SoCs with different values, so just omitting this for the D1 seems odd. Cheers, Andre > + > +unevaluatedProperties: false > + > +required: > + - compatible > + - reg > + - "#pwm-cells" > + - clocks > + - clock-names > + - resets > + > +examples: > + - | > + #include > + #include > + > + pwm: pwm@2000c00 { > + compatible = "allwinner,sun20i-d1-pwm"; > + reg = <0x02000c00 0x400>; > + clocks = <&ccu CLK_BUS_PWM>, <&dcxo>, <&ccu CLK_APB0>; > + clock-names = "bus", "hosc", "apb"; > + resets = <&ccu RST_BUS_PWM>; > + #pwm-cells = <0x3>; > + }; > + > +... _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv