[PATCH v4 0/2] Use GCR.U timer device as clocksource

[PATCH v4 0/2] Use GCR.U timer device as clocksource

[Aleksa Paunovic via B4 Relay]

This series adds bindings for the GCR.U timer device and corresponding
driver support. Accessing the memory mapped mtime register in the GCR.U
region should be faster than trapping to M mode each time the timer
needs to be read.

Changes in v4:
- Remove "select" from mti,gcru.yaml.
- Refactor the driver to use function pointers instead of static keys.

Previous versions:
v1: https://lore.kernel.org/lkml/20241227150056.191794-1-arikalo@gmail.com/#t
v2: https://lore.kernel.org/linux-riscv/20250409143816.15802-1-aleksa.paunovic@htecgroup.com/
v3: https://lore.kernel.org/linux-riscv/DU0PR09MB61968695A2A3146EE83B7708F6BA2@DU0PR09MB6196.eurprd09.prod.outlook.com/

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
Aleksa Paunovic (2):
      dt-bindings: timer: mti,gcru
      Allow for riscv-clock to pick up mmio address.

 .../devicetree/bindings/timer/mti,gcru.yaml        | 38 ++++++++++++++
 arch/riscv/include/asm/timex.h                     | 48 ++++++-----------
 drivers/clocksource/Kconfig                        | 12 +++++
 drivers/clocksource/timer-riscv.c                  | 61 ++++++++++++++++++++++
 4 files changed, 126 insertions(+), 33 deletions(-)
---
base-commit: 9c32cda43eb78f78c73aee4aa344b777714e259b
change-id: 20250424-riscv-time-mmio-5628e0fca8af

Best regards,
-- 
Aleksa Paunovic <aleksa.paunovic@htecgroup.com>



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[PATCH v4 1/2] dt-bindings: timer: mti,gcru

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Add dt-bindings for the GCR.U memory mapped timer device for RISC-V
platforms. The GCR.U memory region contains shadow copies of the RISC-V
mtime register and the hrtime Global Configuration Register.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 .../devicetree/bindings/timer/mti,gcru.yaml        | 38 ++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/timer/mti,gcru.yaml b/Documentation/devicetree/bindings/timer/mti,gcru.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..ceaf90bad5332b64f3c1f28bebdc28d78443898a
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/mti,gcru.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/mti,gcru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GCR.U timer device for RISC-V platforms
+
+maintainers:
+  - Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
+
+description:
+  The GCR.U memory region contains memory mapped shadow copies of
+  mtime and hrtime Global Configuration Registers,
+  which software can choose to make accessible from user mode.
+
+properties:
+  compatible:
+    const: mti,gcru
+
+  reg:
+    items:
+      - description: Read-only shadow copy of the RISC-V mtime register.
+      - description: Read-only shadow copy of the high resolution timer register.
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    timer@1617f000 {
+        compatible = "mti,gcru";
+        reg = <0x1617f050 0x8>,
+              <0x1617f090 0x8>;
+    };

-- 
2.34.1



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Re: [PATCH v4 1/2] dt-bindings: timer: mti,gcru

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 475 bytes --]

On Wed, May 14, 2025 at 10:51:50AM +0200, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> 
> Add dt-bindings for the GCR.U memory mapped timer device for RISC-V
> platforms. The GCR.U memory region contains shadow copies of the RISC-V
> mtime register and the hrtime Global Configuration Register.
> 
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

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[PATCH v4 2/2] Allow for riscv-clock to pick up mmio address.

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Allow faster rdtime access via GCR.U mtime shadow register on RISC-V
devices. This feature can be enabled by setting GCRU_TIME_MMIO during configuration.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 arch/riscv/include/asm/timex.h    | 48 ++++++++++--------------------
 drivers/clocksource/Kconfig       | 12 ++++++++
 drivers/clocksource/timer-riscv.c | 61 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 88 insertions(+), 33 deletions(-)

diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
index a06697846e69521caceac2ae4d4e040d227d2ae7..2dea35fe32c0b080ff27587088bbbe01fad22ce6 100644
--- a/arch/riscv/include/asm/timex.h
+++ b/arch/riscv/include/asm/timex.h
@@ -7,31 +7,25 @@
 #define _ASM_RISCV_TIMEX_H
 
 #include <asm/csr.h>
+#include <asm/mmio.h>
+
+#include <linux/jump_label.h>
 
 typedef unsigned long cycles_t;
 
+extern u64 __iomem *riscv_time_val;
+extern cycles_t (*get_cycles_ptr)(void);
+extern u32 (*get_cycles_hi_ptr)(void);
+
+#define riscv_time_val riscv_time_val
+
 #ifdef CONFIG_RISCV_M_MODE
 
 #include <asm/clint.h>
 
-#ifdef CONFIG_64BIT
-static inline cycles_t get_cycles(void)
-{
-	return readq_relaxed(clint_time_val);
-}
-#else /* !CONFIG_64BIT */
-static inline u32 get_cycles(void)
-{
-	return readl_relaxed(((u32 *)clint_time_val));
-}
-#define get_cycles get_cycles
+#undef riscv_time_val
 
-static inline u32 get_cycles_hi(void)
-{
-	return readl_relaxed(((u32 *)clint_time_val) + 1);
-}
-#define get_cycles_hi get_cycles_hi
-#endif /* CONFIG_64BIT */
+#define riscv_time_val clint_time_val
 
 /*
  * Much like MIPS, we may not have a viable counter to use at an early point
@@ -45,29 +39,17 @@ static inline unsigned long random_get_entropy(void)
 	return get_cycles();
 }
 #define random_get_entropy()	random_get_entropy()
+#endif
 
-#else /* CONFIG_RISCV_M_MODE */
-
-static inline cycles_t get_cycles(void)
-{
-	return csr_read(CSR_TIME);
-}
-#define get_cycles get_cycles
-
-static inline u32 get_cycles_hi(void)
-{
-	return csr_read(CSR_TIMEH);
-}
-#define get_cycles_hi get_cycles_hi
-
-#endif /* !CONFIG_RISCV_M_MODE */
+#define get_cycles get_cycles_ptr
+#define get_cycles_hi get_cycles_ptr_hi
 
 #ifdef CONFIG_64BIT
 static inline u64 get_cycles64(void)
 {
 	return get_cycles();
 }
-#else /* CONFIG_64BIT */
+#else /* !CONFIG_64BIT */
 static inline u64 get_cycles64(void)
 {
 	u32 hi, lo;
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 487c8525996724fbf9c6e9726dabb478d86513b9..0f2bb75564c7d2bc9c450a7fb0eef353e5d27e69 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -661,6 +661,18 @@ config CLINT_TIMER
 	  This option enables the CLINT timer for RISC-V systems.  The CLINT
 	  driver is usually used for NoMMU RISC-V systems.
 
+config GCRU_TIME_MMIO
+	bool "GCR.U timer support for RISC-V platforms"
+	depends on !RISCV_M_MODE && RISCV
+	default n
+	help
+        Access GCR.U shadow copy of the RISC-V mtime register
+        on platforms that provide a compatible device, instead of
+        reading the time CSR. Since reading the time CSR
+        traps to M mode on certain platforms, this may be more efficient.
+
+        If you don't know what to do here, say n.
+
 config CSKY_MP_TIMER
 	bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
 	depends on CSKY
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 4d7cf338824a3b21461c2756a002236dedc48f5f..1ccf2a95f5bcb28946dcee435f5bbea222c6fac3 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -22,6 +22,7 @@
 #include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/interrupt.h>
 #include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <linux/limits.h>
 #include <clocksource/timer-riscv.h>
 #include <asm/smp.h>
@@ -32,6 +33,42 @@
 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
 static bool riscv_timer_cannot_wake_cpu;
 
+u64 __iomem *riscv_time_val __ro_after_init;
+EXPORT_SYMBOL(riscv_time_val);
+
+#ifdef CONFIG_64BIT
+static cycles_t __maybe_unused mmio_get_cycles(void)
+{
+	return readq_relaxed(riscv_time_val);
+}
+#else /* !CONFIG_64BIT */
+static cycles_t __maybe_unused mmio_get_cycles(void)
+{
+	return readl_relaxed(((u32 *)riscv_time_val));
+}
+#endif /* CONFIG_64BIT */
+
+static cycles_t __maybe_unused get_cycles_csr(void)
+{
+	return csr_read(CSR_TIME);
+}
+
+static u32 __maybe_unused mmio_get_cycles_hi(void)
+{
+	return readl_relaxed(((u32 *)riscv_time_val) + 1);
+}
+
+static u32 __maybe_unused get_cycles_hi_csr(void)
+{
+	return csr_read(CSR_TIMEH);
+}
+
+cycles_t (*get_cycles_ptr)(void) = get_cycles_csr;
+EXPORT_SYMBOL(get_cycles_ptr);
+
+u32 (*get_cycles_hi_ptr)(void) = get_cycles_hi_csr;
+EXPORT_SYMBOL(get_cycles_hi_ptr);
+
 static void riscv_clock_event_stop(void)
 {
 	if (static_branch_likely(&riscv_sstc_available)) {
@@ -209,6 +246,11 @@ static int __init riscv_timer_init_dt(struct device_node *n)
 	int cpuid, error;
 	unsigned long hartid;
 	struct device_node *child;
+#if defined(CONFIG_GCRU_TIME_MMIO)
+	u64 mmio_addr;
+	u64 mmio_size;
+	struct device_node *gcru;
+#endif
 
 	error = riscv_of_processor_hartid(n, &hartid);
 	if (error < 0) {
@@ -226,6 +268,25 @@ static int __init riscv_timer_init_dt(struct device_node *n)
 	if (cpuid != smp_processor_id())
 		return 0;
 
+#if defined(CONFIG_GCRU_TIME_MMIO)
+	gcru = of_find_compatible_node(NULL, NULL, "mti,gcru");
+	if (gcru) {
+		if (!of_property_read_reg(gcru, 0, &mmio_addr, &mmio_size)) {
+			riscv_time_val = ioremap((long)mmio_addr, mmio_size);
+			if (riscv_time_val) {
+				pr_info("Using mmio time register at 0x%llx\n",
+					mmio_addr);
+				get_cycles_ptr = &mmio_get_cycles;
+				get_cycles_hi_ptr = &mmio_get_cycles_hi;
+			} else {
+				pr_warn("Unable to use mmio time at 0x%llx\n",
+					mmio_addr);
+			}
+			of_node_put(gcru);
+		}
+	}
+#endif
+
 	child = of_find_compatible_node(NULL, NULL, "riscv,timer");
 	if (child) {
 		riscv_timer_cannot_wake_cpu = of_property_read_bool(child,

-- 
2.34.1



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Re: [PATCH v4 2/2] Allow for riscv-clock to pick up mmio address.

[kernel test robot]

Hi Aleksa,

kernel test robot noticed the following build errors:

[auto build test ERROR on 9c32cda43eb78f78c73aee4aa344b777714e259b]

url:    https://github.com/intel-lab-lkp/linux/commits/Aleksa-Paunovic-via-B4-Relay/dt-bindings-timer-mti-gcru/20250514-165347
base:   9c32cda43eb78f78c73aee4aa344b777714e259b
patch link:    https://lore.kernel.org/r/20250514-riscv-time-mmio-v4-2-cb0cf2922d66%40htecgroup.com
patch subject: [PATCH v4 2/2] Allow for riscv-clock to pick up mmio address.
config: riscv-randconfig-001-20250515 (https://download.01.org/0day-ci/archive/20250515/202505150913.Iq1XRKqC-lkp@intel.com/config)
compiler: riscv32-linux-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250515/202505150913.Iq1XRKqC-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505150913.Iq1XRKqC-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from include/linux/timex.h:67,
                    from include/linux/time32.h:13,
                    from include/linux/time.h:60,
                    from include/linux/jiffies.h:10,
                    from include/linux/ktime.h:25,
                    from include/linux/timer.h:6,
                    from include/linux/uprobes.h:18,
                    from include/linux/mm_types.h:16,
                    from include/linux/mmzone.h:22,
                    from include/linux/gfp.h:7,
                    from include/linux/mm.h:7,
                    from arch/riscv/kernel/asm-offsets.c:8:
   arch/riscv/include/asm/timex.h: In function 'random_get_entropy':
>> arch/riscv/include/asm/timex.h:39:9: error: implicit declaration of function 'get_cycles'; did you mean 'get_cycles_ptr'? [-Werror=implicit-function-declaration]
     return get_cycles();
            ^~~~~~~~~~
            get_cycles_ptr
   arch/riscv/include/asm/timex.h: In function 'get_cycles64':
>> arch/riscv/include/asm/timex.h:45:23: error: implicit declaration of function 'get_cycles_ptr_hi'; did you mean 'get_cycles_ptr'? [-Werror=implicit-function-declaration]
    #define get_cycles_hi get_cycles_ptr_hi
                          ^~~~~~~~~~~~~~~~~
   arch/riscv/include/asm/timex.h:58:8: note: in expansion of macro 'get_cycles_hi'
      hi = get_cycles_hi();
           ^~~~~~~~~~~~~
   cc1: some warnings being treated as errors
   make[3]: *** [scripts/Makefile.build:98: arch/riscv/kernel/asm-offsets.s] Error 1 shuffle=2386734513
   make[3]: Target 'prepare' not remade because of errors.
   make[2]: *** [Makefile:1282: prepare0] Error 2 shuffle=2386734513
   make[2]: Target 'prepare' not remade because of errors.
   make[1]: *** [Makefile:248: __sub-make] Error 2 shuffle=2386734513
   make[1]: Target 'prepare' not remade because of errors.
   make: *** [Makefile:248: __sub-make] Error 2 shuffle=2386734513
   make: Target 'prepare' not remade because of errors.


vim +39 arch/riscv/include/asm/timex.h

d5be89a8d118a8 Palmer Dabbelt     2020-09-14  29  
aa9887608e77b8 Anup Patel         2020-09-27  30  /*
aa9887608e77b8 Anup Patel         2020-09-27  31   * Much like MIPS, we may not have a viable counter to use at an early point
aa9887608e77b8 Anup Patel         2020-09-27  32   * in the boot process. Unfortunately we don't have a fallback, so instead
aa9887608e77b8 Anup Patel         2020-09-27  33   * we just return 0.
aa9887608e77b8 Anup Patel         2020-09-27  34   */
aa9887608e77b8 Anup Patel         2020-09-27  35  static inline unsigned long random_get_entropy(void)
aa9887608e77b8 Anup Patel         2020-09-27  36  {
aa9887608e77b8 Anup Patel         2020-09-27  37  	if (unlikely(clint_time_val == NULL))
6d01238623faa9 Jason A. Donenfeld 2022-04-08  38  		return random_get_entropy_fallback();
aa9887608e77b8 Anup Patel         2020-09-27 @39  	return get_cycles();
aa9887608e77b8 Anup Patel         2020-09-27  40  }
aa9887608e77b8 Anup Patel         2020-09-27  41  #define random_get_entropy()	random_get_entropy()
7eeda0113dff84 Aleksa Paunovic    2025-05-14  42  #endif
aa9887608e77b8 Anup Patel         2020-09-27  43  
7eeda0113dff84 Aleksa Paunovic    2025-05-14  44  #define get_cycles get_cycles_ptr
7eeda0113dff84 Aleksa Paunovic    2025-05-14 @45  #define get_cycles_hi get_cycles_ptr_hi
ccbbfd1cbf365b Palmer Dabbelt     2020-11-25  46  

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Re: [PATCH v4 2/2] Allow for riscv-clock to pick up mmio address.

[kernel test robot]

Hi Aleksa,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 9c32cda43eb78f78c73aee4aa344b777714e259b]

url:    https://github.com/intel-lab-lkp/linux/commits/Aleksa-Paunovic-via-B4-Relay/dt-bindings-timer-mti-gcru/20250514-165347
base:   9c32cda43eb78f78c73aee4aa344b777714e259b
patch link:    https://lore.kernel.org/r/20250514-riscv-time-mmio-v4-2-cb0cf2922d66%40htecgroup.com
patch subject: [PATCH v4 2/2] Allow for riscv-clock to pick up mmio address.
config: riscv-randconfig-r121-20250520 (https://download.01.org/0day-ci/archive/20250520/202505200822.Av88hkk5-lkp@intel.com/config)
compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90)
reproduce: (https://download.01.org/0day-ci/archive/20250520/202505200822.Av88hkk5-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505200822.Av88hkk5-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
   WARNING: invalid argument to '-march': '_zabha'
>> drivers/clocksource/timer-riscv.c:58:16: sparse: sparse: cast removes address space '__iomem' of expression
>> drivers/clocksource/timer-riscv.c:58:16: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *addr @@     got unsigned int [usertype] * @@
   drivers/clocksource/timer-riscv.c:58:16: sparse:     expected void const volatile [noderef] __iomem *addr
   drivers/clocksource/timer-riscv.c:58:16: sparse:     got unsigned int [usertype] *

vim +/__iomem +58 drivers/clocksource/timer-riscv.c

    55	
    56	static u32 __maybe_unused mmio_get_cycles_hi(void)
    57	{
  > 58		return readl_relaxed(((u32 *)riscv_time_val) + 1);
    59	}
    60	

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Re: [PATCH v4 2/2] Allow for riscv-clock to pick up mmio address.

[Alexandre Ghiti]

Hi Aleksa,

First, you commit title should be prefixed with "riscv:".

On 5/14/25 10:51, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>
> Allow faster rdtime access via GCR.U mtime shadow register on RISC-V
> devices. This feature can be enabled by setting GCRU_TIME_MMIO during configuration.


What's GCR.U? I can't find anything online. Conor asked something 
similar in v2 btw.


>
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>   arch/riscv/include/asm/timex.h    | 48 ++++++++++--------------------
>   drivers/clocksource/Kconfig       | 12 ++++++++
>   drivers/clocksource/timer-riscv.c | 61 +++++++++++++++++++++++++++++++++++++++
>   3 files changed, 88 insertions(+), 33 deletions(-)
>
> diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
> index a06697846e69521caceac2ae4d4e040d227d2ae7..2dea35fe32c0b080ff27587088bbbe01fad22ce6 100644
> --- a/arch/riscv/include/asm/timex.h
> +++ b/arch/riscv/include/asm/timex.h
> @@ -7,31 +7,25 @@
>   #define _ASM_RISCV_TIMEX_H
>   
>   #include <asm/csr.h>
> +#include <asm/mmio.h>
> +
> +#include <linux/jump_label.h>
>   
>   typedef unsigned long cycles_t;
>   
> +extern u64 __iomem *riscv_time_val;
> +extern cycles_t (*get_cycles_ptr)(void);
> +extern u32 (*get_cycles_hi_ptr)(void);
> +
> +#define riscv_time_val riscv_time_val


As already mentioned by Daniel, this is weird ^, why don't you just 
initialize riscv_time_val with the mmio address?


> +
>   #ifdef CONFIG_RISCV_M_MODE
>   
>   #include <asm/clint.h>
>   
> -#ifdef CONFIG_64BIT
> -static inline cycles_t get_cycles(void)
> -{
> -	return readq_relaxed(clint_time_val);
> -}
> -#else /* !CONFIG_64BIT */
> -static inline u32 get_cycles(void)
> -{
> -	return readl_relaxed(((u32 *)clint_time_val));
> -}
> -#define get_cycles get_cycles
> +#undef riscv_time_val
>   
> -static inline u32 get_cycles_hi(void)
> -{
> -	return readl_relaxed(((u32 *)clint_time_val) + 1);
> -}
> -#define get_cycles_hi get_cycles_hi
> -#endif /* CONFIG_64BIT */
> +#define riscv_time_val clint_time_val


Yes, I would remove that too.


>   
>   /*
>    * Much like MIPS, we may not have a viable counter to use at an early point
> @@ -45,29 +39,17 @@ static inline unsigned long random_get_entropy(void)
>   	return get_cycles();
>   }
>   #define random_get_entropy()	random_get_entropy()
> +#endif
>   
> -#else /* CONFIG_RISCV_M_MODE */
> -
> -static inline cycles_t get_cycles(void)
> -{
> -	return csr_read(CSR_TIME);
> -}
> -#define get_cycles get_cycles
> -
> -static inline u32 get_cycles_hi(void)
> -{
> -	return csr_read(CSR_TIMEH);
> -}
> -#define get_cycles_hi get_cycles_hi
> -
> -#endif /* !CONFIG_RISCV_M_MODE */
> +#define get_cycles get_cycles_ptr
> +#define get_cycles_hi get_cycles_ptr_hi
>   
>   #ifdef CONFIG_64BIT
>   static inline u64 get_cycles64(void)
>   {
>   	return get_cycles();
>   }
> -#else /* CONFIG_64BIT */
> +#else /* !CONFIG_64BIT */
>   static inline u64 get_cycles64(void)
>   {
>   	u32 hi, lo;
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 487c8525996724fbf9c6e9726dabb478d86513b9..0f2bb75564c7d2bc9c450a7fb0eef353e5d27e69 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -661,6 +661,18 @@ config CLINT_TIMER
>   	  This option enables the CLINT timer for RISC-V systems.  The CLINT
>   	  driver is usually used for NoMMU RISC-V systems.
>   
> +config GCRU_TIME_MMIO
> +	bool "GCR.U timer support for RISC-V platforms"
> +	depends on !RISCV_M_MODE && RISCV


Here you depend on dt (Conor asked for this change in v2).


> +	default n
> +	help
> +        Access GCR.U shadow copy of the RISC-V mtime register
> +        on platforms that provide a compatible device, instead of
> +        reading the time CSR. Since reading the time CSR
> +        traps to M mode on certain platforms, this may be more efficient.
> +
> +        If you don't know what to do here, say n.
> +
>   config CSKY_MP_TIMER
>   	bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
>   	depends on CSKY
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 4d7cf338824a3b21461c2756a002236dedc48f5f..1ccf2a95f5bcb28946dcee435f5bbea222c6fac3 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -22,6 +22,7 @@
>   #include <linux/io-64-nonatomic-lo-hi.h>
>   #include <linux/interrupt.h>
>   #include <linux/of_irq.h>
> +#include <linux/of_address.h>
>   #include <linux/limits.h>
>   #include <clocksource/timer-riscv.h>
>   #include <asm/smp.h>
> @@ -32,6 +33,42 @@
>   static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
>   static bool riscv_timer_cannot_wake_cpu;
>   
> +u64 __iomem *riscv_time_val __ro_after_init;
> +EXPORT_SYMBOL(riscv_time_val);
> +
> +#ifdef CONFIG_64BIT
> +static cycles_t __maybe_unused mmio_get_cycles(void)
> +{
> +	return readq_relaxed(riscv_time_val);
> +}
> +#else /* !CONFIG_64BIT */
> +static cycles_t __maybe_unused mmio_get_cycles(void)
> +{
> +	return readl_relaxed(((u32 *)riscv_time_val));
> +}
> +#endif /* CONFIG_64BIT */
> +
> +static cycles_t __maybe_unused get_cycles_csr(void)
> +{
> +	return csr_read(CSR_TIME);
> +}
> +
> +static u32 __maybe_unused mmio_get_cycles_hi(void)
> +{
> +	return readl_relaxed(((u32 *)riscv_time_val) + 1);
> +}
> +
> +static u32 __maybe_unused get_cycles_hi_csr(void)
> +{
> +	return csr_read(CSR_TIMEH);
> +}
> +
> +cycles_t (*get_cycles_ptr)(void) = get_cycles_csr;
> +EXPORT_SYMBOL(get_cycles_ptr);
> +
> +u32 (*get_cycles_hi_ptr)(void) = get_cycles_hi_csr;
> +EXPORT_SYMBOL(get_cycles_hi_ptr);
> +
>   static void riscv_clock_event_stop(void)
>   {
>   	if (static_branch_likely(&riscv_sstc_available)) {
> @@ -209,6 +246,11 @@ static int __init riscv_timer_init_dt(struct device_node *n)
>   	int cpuid, error;
>   	unsigned long hartid;
>   	struct device_node *child;
> +#if defined(CONFIG_GCRU_TIME_MMIO)
> +	u64 mmio_addr;
> +	u64 mmio_size;
> +	struct device_node *gcru;
> +#endif
>   
>   	error = riscv_of_processor_hartid(n, &hartid);
>   	if (error < 0) {
> @@ -226,6 +268,25 @@ static int __init riscv_timer_init_dt(struct device_node *n)
>   	if (cpuid != smp_processor_id())
>   		return 0;
>   
> +#if defined(CONFIG_GCRU_TIME_MMIO)
> +	gcru = of_find_compatible_node(NULL, NULL, "mti,gcru");
> +	if (gcru) {
> +		if (!of_property_read_reg(gcru, 0, &mmio_addr, &mmio_size)) {
> +			riscv_time_val = ioremap((long)mmio_addr, mmio_size);
> +			if (riscv_time_val) {
> +				pr_info("Using mmio time register at 0x%llx\n",
> +					mmio_addr);
> +				get_cycles_ptr = &mmio_get_cycles;
> +				get_cycles_hi_ptr = &mmio_get_cycles_hi;
> +			} else {
> +				pr_warn("Unable to use mmio time at 0x%llx\n",
> +					mmio_addr);
> +			}
> +			of_node_put(gcru);
> +		}
> +	}
> +#endif
> +
>   	child = of_find_compatible_node(NULL, NULL, "riscv,timer");
>   	if (child) {
>   		riscv_timer_cannot_wake_cpu = of_property_read_bool(child,


And you have a bunch of kernel test robot failures to fix too :)

Thanks,

Alex



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Re: [PATCH v4 2/2] Allow for riscv-clock to pick up mmio address.

[Aleksa Paunovic]

Hello Alexandre,

Thank you for your suggestions!


On 21. 5. 25. 12:43, Alexandre Ghiti wrote:

> 
> Hi Aleksa,
> 
> First, you commit title should be prefixed with "riscv:".
> 
> On 5/14/25 10:51, Aleksa Paunovic via B4 Relay wrote:
>> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>>
>> Allow faster rdtime access via GCR.U mtime shadow register on RISC-V
>> devices. This feature can be enabled by setting GCRU_TIME_MMIO during configuration.
> 
> 
> What's GCR.U? I can't find anything online. Conor asked something
> similar in v2 btw.
>  

Please see [1] for more details, especially the "GCR.U User Mode Registers" section. Essentially, it's a user-accessible memory region holding shadow copies of some M mode registers. Since both of these registers are time-related, we decided to register it as a timer device. The example in the first patch of the series is taken from the .dts file for the p8700 cpu.

[1]
https://mips.com/wp-content/uploads/2025/04/P8700-F_Programmers_Reference_Manual_Rev1.83_4-9-2025.pdf

> 
>>
>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>> ---
>>   arch/riscv/include/asm/timex.h    | 48 ++++++++++--------------------
>>   drivers/clocksource/Kconfig       | 12 ++++++++
>>   drivers/clocksource/timer-riscv.c | 61 +++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 88 insertions(+), 33 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
>> index a06697846e69521caceac2ae4d4e040d227d2ae7..2dea35fe32c0b080ff27587088bbbe01fad22ce6 100644
>> --- a/arch/riscv/include/asm/timex.h
>> +++ b/arch/riscv/include/asm/timex.h
>> @@ -7,31 +7,25 @@
>>   #define _ASM_RISCV_TIMEX_H
>>
>>   #include <asm/csr.h>
>> +#include <asm/mmio.h>
>> +
>> +#include <linux/jump_label.h>
>>
>>   typedef unsigned long cycles_t;
>>
>> +extern u64 __iomem *riscv_time_val;
>> +extern cycles_t (*get_cycles_ptr)(void);
>> +extern u32 (*get_cycles_hi_ptr)(void);
>> +
>> +#define riscv_time_val riscv_time_val
> 
> 
> As already mentioned by Daniel, this is weird ^, why don't you just
> initialize riscv_time_val with the mmio address?
>  

Simply initializing risv_time_val doesn't work, since we need to read the mmio address from the device tree. 

Will apply other requested changes in v5 of the series. 

Best regards,
Aleksa

> 
>> +
>>   #ifdef CONFIG_RISCV_M_MODE
>>
>>   #include <asm/clint.h>
>>
>> -#ifdef CONFIG_64BIT
>> -static inline cycles_t get_cycles(void)
>> -{
>> -     return readq_relaxed(clint_time_val);
>> -}
>> -#else /* !CONFIG_64BIT */
>> -static inline u32 get_cycles(void)
>> -{
>> -     return readl_relaxed(((u32 *)clint_time_val));
>> -}
>> -#define get_cycles get_cycles
>> +#undef riscv_time_val
>>
>> -static inline u32 get_cycles_hi(void)
>> -{
>> -     return readl_relaxed(((u32 *)clint_time_val) + 1);
>> -}
>> -#define get_cycles_hi get_cycles_hi
>> -#endif /* CONFIG_64BIT */
>> +#define riscv_time_val clint_time_val
> 
> 
> Yes, I would remove that too.
> 
> 
>>
>>   /*
>>    * Much like MIPS, we may not have a viable counter to use at an early point
>> @@ -45,29 +39,17 @@ static inline unsigned long random_get_entropy(void)
>>       return get_cycles();
>>   }
>>   #define random_get_entropy()        random_get_entropy()
>> +#endif
>>
>> -#else /* CONFIG_RISCV_M_MODE */
>> -
>> -static inline cycles_t get_cycles(void)
>> -{
>> -     return csr_read(CSR_TIME);
>> -}
>> -#define get_cycles get_cycles
>> -
>> -static inline u32 get_cycles_hi(void)
>> -{
>> -     return csr_read(CSR_TIMEH);
>> -}
>> -#define get_cycles_hi get_cycles_hi
>> -
>> -#endif /* !CONFIG_RISCV_M_MODE */
>> +#define get_cycles get_cycles_ptr
>> +#define get_cycles_hi get_cycles_ptr_hi
>>
>>   #ifdef CONFIG_64BIT
>>   static inline u64 get_cycles64(void)
>>   {
>>       return get_cycles();
>>   }
>> -#else /* CONFIG_64BIT */
>> +#else /* !CONFIG_64BIT */
>>   static inline u64 get_cycles64(void)
>>   {
>>       u32 hi, lo;
>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
>> index 487c8525996724fbf9c6e9726dabb478d86513b9..0f2bb75564c7d2bc9c450a7fb0eef353e5d27e69 100644
>> --- a/drivers/clocksource/Kconfig
>> +++ b/drivers/clocksource/Kconfig
>> @@ -661,6 +661,18 @@ config CLINT_TIMER
>>         This option enables the CLINT timer for RISC-V systems.  The CLINT
>>         driver is usually used for NoMMU RISC-V systems.
>>
>> +config GCRU_TIME_MMIO
>> +     bool "GCR.U timer support for RISC-V platforms"
>> +     depends on !RISCV_M_MODE && RISCV
> 
> 
> Here you depend on dt (Conor asked for this change in v2).
> 
> 
>> +     default n
>> +     help
>> +        Access GCR.U shadow copy of the RISC-V mtime register
>> +        on platforms that provide a compatible device, instead of
>> +        reading the time CSR. Since reading the time CSR
>> +        traps to M mode on certain platforms, this may be more efficient.
>> +
>> +        If you don't know what to do here, say n.
>> +
>>   config CSKY_MP_TIMER
>>       bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
>>       depends on CSKY
>> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
>> index 4d7cf338824a3b21461c2756a002236dedc48f5f..1ccf2a95f5bcb28946dcee435f5bbea222c6fac3 100644
>> --- a/drivers/clocksource/timer-riscv.c
>> +++ b/drivers/clocksource/timer-riscv.c
>> @@ -22,6 +22,7 @@
>>   #include <linux/io-64-nonatomic-lo-hi.h>
>>   #include <linux/interrupt.h>
>>   #include <linux/of_irq.h>
>> +#include <linux/of_address.h>
>>   #include <linux/limits.h>
>>   #include <clocksource/timer-riscv.h>
>>   #include <asm/smp.h>
>> @@ -32,6 +33,42 @@
>>   static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
>>   static bool riscv_timer_cannot_wake_cpu;
>>
>> +u64 __iomem *riscv_time_val __ro_after_init;
>> +EXPORT_SYMBOL(riscv_time_val);
>> +
>> +#ifdef CONFIG_64BIT
>> +static cycles_t __maybe_unused mmio_get_cycles(void)
>> +{
>> +     return readq_relaxed(riscv_time_val);
>> +}
>> +#else /* !CONFIG_64BIT */
>> +static cycles_t __maybe_unused mmio_get_cycles(void)
>> +{
>> +     return readl_relaxed(((u32 *)riscv_time_val));
>> +}
>> +#endif /* CONFIG_64BIT */
>> +
>> +static cycles_t __maybe_unused get_cycles_csr(void)
>> +{
>> +     return csr_read(CSR_TIME);
>> +}
>> +
>> +static u32 __maybe_unused mmio_get_cycles_hi(void)
>> +{
>> +     return readl_relaxed(((u32 *)riscv_time_val) + 1);
>> +}
>> +
>> +static u32 __maybe_unused get_cycles_hi_csr(void)
>> +{
>> +     return csr_read(CSR_TIMEH);
>> +}
>> +
>> +cycles_t (*get_cycles_ptr)(void) = get_cycles_csr;
>> +EXPORT_SYMBOL(get_cycles_ptr);
>> +
>> +u32 (*get_cycles_hi_ptr)(void) = get_cycles_hi_csr;
>> +EXPORT_SYMBOL(get_cycles_hi_ptr);
>> +
>>   static void riscv_clock_event_stop(void)
>>   {
>>       if (static_branch_likely(&riscv_sstc_available)) {
>> @@ -209,6 +246,11 @@ static int __init riscv_timer_init_dt(struct device_node *n)
>>       int cpuid, error;
>>       unsigned long hartid;
>>       struct device_node *child;
>> +#if defined(CONFIG_GCRU_TIME_MMIO)
>> +     u64 mmio_addr;
>> +     u64 mmio_size;
>> +     struct device_node *gcru;
>> +#endif
>>
>>       error = riscv_of_processor_hartid(n, &hartid);
>>       if (error < 0) {
>> @@ -226,6 +268,25 @@ static int __init riscv_timer_init_dt(struct device_node *n)
>>       if (cpuid != smp_processor_id())
>>               return 0;
>>
>> +#if defined(CONFIG_GCRU_TIME_MMIO)
>> +     gcru = of_find_compatible_node(NULL, NULL, "mti,gcru");
>> +     if (gcru) {
>> +             if (!of_property_read_reg(gcru, 0, &mmio_addr, &mmio_size)) {
>> +                     riscv_time_val = ioremap((long)mmio_addr, mmio_size);
>> +                     if (riscv_time_val) {
>> +                             pr_info("Using mmio time register at 0x%llx\n",
>> +                                     mmio_addr);
>> +                             get_cycles_ptr = &mmio_get_cycles;
>> +                             get_cycles_hi_ptr = &mmio_get_cycles_hi;
>> +                     } else {
>> +                             pr_warn("Unable to use mmio time at 0x%llx\n",
>> +                                     mmio_addr);
>> +                     }
>> +                     of_node_put(gcru);
>> +             }
>> +     }
>> +#endif
>> +
>>       child = of_find_compatible_node(NULL, NULL, "riscv,timer");
>>       if (child) {
>>               riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
> 
> 
> And you have a bunch of kernel test robot failures to fix too :)
> 
> Thanks,
> 
> Alex
> 
> 
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