* [GIT PULL 3/3] RISC-V Devicetrees for v6.16
@ 2025-05-16 11:01 Conor Dooley
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From: Conor Dooley @ 2025-05-16 11:01 UTC (permalink / raw)
To: soc; +Cc: conor, linux-riscv
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Hey Arnd
Please pull some ~RISC-V~Starfive updates for 6.16. They're a bit late
and only went into linux-next today, cos I was stalling out for some
acks before picking them up.
Thanks,
Conor.
The following changes since commit 0af2f6be1b4281385b618cb86ad946eded089ac8:
Linux 6.15-rc1 (2025-04-06 13:11:33 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-dt-for-v6.16
for you to fetch changes up to d50108706a63dfd896db42172bf9f6aebec219c5:
riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader (2025-05-15 21:08:27 +0100)
----------------------------------------------------------------
RISC-V Devicetrees for v6.16
Starfive:
All Starfive this time (again), enabling the usb3 port on the framework
laptop mainboard, and a few cleanup patches that are syncing things with
the dts used by U-Boot.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
----------------------------------------------------------------
E Shattow (4):
riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader
Icenowy Zheng (1):
riscv: dts: starfive: jh7110-common: use macros for MMC0 pins
Sandie Cao (1):
riscv: dts: starfive: fml13v01: enable USB 3.0 port
arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 52 ++++++++++++++++------
.../dts/starfive/jh7110-deepcomputing-fml13v01.dts | 19 ++++++++
2 files changed, 57 insertions(+), 14 deletions(-)
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2025-05-16 11:01 [GIT PULL 3/3] RISC-V Devicetrees for v6.16 Conor Dooley
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