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From: E Shattow <e@freeshell.de>
To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, Conor Dooley <conor@kernel.org>,
	Emil Renner Berthing <kernel@esmil.dk>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>
Cc: E Shattow <e@freeshell.de>
Subject: [PATCH v1 2/3] riscv: dts: starfive: jh7110: add memory controller node
Date: Fri,  6 Jun 2025 06:02:37 -0700	[thread overview]
Message-ID: <20250606130253.1105273-3-e@freeshell.de> (raw)
In-Reply-To: <20250606130253.1105273-1-e@freeshell.de>

add memory controller node used downstream by U-Boot boot loader.

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0ba74ef04679..6fdeac3e0aff 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -372,6 +372,19 @@ ccache: cache-controller@2010000 {
 			cache-unified;
 		};
 
+		memory-controller@15700000 {
+			compatible = "starfive,jh7110-dmc";
+			reg = <0x0 0x15700000 0x0 0x10000>,
+			      <0x0 0x13000000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+			clock-names = "pll1_out";
+			clock-frequency = <2133>;
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				 <&syscrg JH7110_SYSRST_DDR_OSC>,
+				 <&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+		};
+
 		plic: interrupt-controller@c000000 {
 			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
-- 
2.49.0


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  parent reply	other threads:[~2025-06-06 13:04 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-06 13:02 [PATCH v1 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow
2025-06-06 13:02 ` [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC E Shattow
2025-06-23  6:44   ` Krzysztof Kozlowski
2025-06-23  6:45   ` Krzysztof Kozlowski
2025-06-23 15:56     ` Conor Dooley
2025-06-23 16:11       ` Krzysztof Kozlowski
2025-06-06 13:02 ` E Shattow [this message]
2025-06-06 13:02 ` [PATCH v1 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader E Shattow

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