From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11416C71135 for ; Sun, 15 Jun 2025 18:49:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ufN+1fPH5n9ej3Vheex0koAF+CjHwc3RD/pVfts7tHA=; b=FmAwtRA6W7cDBY 3u8sNac/HKzttXjvZT38oHMCn066Q6i/sp1LAkdpOhzMcVEpuspHzYhykW+2ql+54yfocGekrAuZf YExi4LF1oS8Hiw0fbsDVsylb72aVOIhcXxuA0ht4BaocbV2rvhrxMscNCaYwFjiOyof9vaMzEJaS4 8s7TdesIKqnldIuV1dOmsPg/47J8d+gdRKgbQ6QZb41r7qvwR7A6dlmpBxdiCeGWX+ZWqP5NeYXPN HsZODgnp8Fv0EVRDNHRQxokccJqwOpb9nNwa39IKsugYOaBEuEVg1F2a785bLSe3suB0S+nxuLS1K BoWD3P7w1KpqrC62B7Bw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uQsQ1-00000002kcc-24hg; Sun, 15 Jun 2025 18:49:25 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uQsNm-00000002kQZ-3YXO; Sun, 15 Jun 2025 18:47:08 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 2BC534AB32; Sun, 15 Jun 2025 18:47:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AA633C4CEE3; Sun, 15 Jun 2025 18:47:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750013226; bh=5b3uNryP074LRzS0e8lRw21Ibl8znCFGJk8dG32zXQw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=dBPtFxhSJMUXxmaT/KxQ35nsgIcXL/g9ImLlDTQb++SUrhRAv5BrYEyhMzlivQTnA b5r6qgTgn/HKGqJKv8iIJZIrBrbSU8quRUHzUx02dyadCT/fXANUmLE4BYuuyerOk5 syWDFFmKz8D7g32RagfLqYXxRSTC1HcHir74l/R1J5sHSjE1peKYYs60gZCL3eQPFb cTq1v0r+DKJnH6n9ApPtKk3wepQy940tpEOG1qlya7EY3CViKAzbLFJr2wnU1AGoVG WMCEPfl0m7mcUWeu5p5Yg2rrbz49hc8W2AJ7VRhT2wOOyNch3zWfyN/nLXRv7u5Cna suPZqRSuvlvJQ== Date: Sun, 15 Jun 2025 11:46:38 -0700 From: Eric Biggers To: Ard Biesheuvel Cc: Herbert Xu , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, x86@kernel.org, Jason@zx2c4.com, torvalds@linux-foundation.org Subject: Re: [PATCH] crypto: ahash - Stop legacy tfms from using the set_virt fallback path Message-ID: <20250615184638.GA1480@sol> References: <20250611033957.GA1484147@sol> <20250611035842.GB1484147@sol> <20250613053624.GA163131@sol> <20250613055439.GB163131@sol> <20250615031807.GA81869@sol> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250615_114706_915477_6AC04482 X-CRM114-Status: GOOD ( 28.94 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, Jun 15, 2025 at 09:22:51AM +0200, Ard Biesheuvel wrote: > On Sun, 15 Jun 2025 at 05:18, Eric Biggers wrote: > > > ... > > After disabling the crypto self-tests, I was then able to run a benchmark of > > SHA-256 hashing 4096-byte messages, which fortunately didn't encounter the > > recursion bug. I got the following results: > > > > ARMv8 crypto extensions: 1864 MB/s > > Generic C code: 358 MB/s > > Qualcomm Crypto Engine: 55 MB/s > > > > So just to clarify, you believe that asynchronous hash drivers like the Qualcomm > > Crypto Engine one are useful, and the changes that you're requiring to the > > CPU-based code are to support these drivers? > > > > And this offload engine only has one internal queue, right? Whereas > the CPU results may be multiplied by the number of cores on the soc. > It would still be interesting how much of this is due to latency > rather than limited throughput but it seems highly unlikely that there > are any message sizes large enough where QCE would catch up with the > CPUs. (AIUI, the only use case we have in the kernel today for message > sizes that are substantially larger than this is kTLS, but I'm not > sure how well it works with crypto_aead compared to offload at a more > suitable level in the networking stack, and this driver does not > implement GCM in the first place) > > On ARM socs, these offload engines usually exist primarily for the > benefit of the verified boot implementation in mask ROM, which > obviously needs to be minimal but doesn't have to be very fast in > order to get past the first boot stages and hand over to software. > Then, since the IP block is there, it's listed as a feature in the > data sheet, even though it is not very useful when running under the > OS. With 1 MiB messages, I get 1913 MB/s with ARMv8 CE and 142 MB/s with QCE. (BTW, that's single-buffer ARMv8 CE. My two-buffer code is over 3000 MB/s.) I then changed my benchmark code to take full advantage of the async API and submit as many requests as the hardware can handle. (This would be a best-case scenario for QCE; in many real use cases this is not possible.) Result with QCE was 58 MB/s with 4 KiB messages or 155 MB/s for 1 MiB messages. So yes, QCE seems to have only one queue, and even that one queue is *much* slower than just using the CPU. It's even slower than the generic C code. And until I fixed it recently, the Crypto API defaulted to using QCE instead of ARMv8 CE. But this seems to be a common pattern among the offload engines. I noticed a similar issue with Intel QAT, which I elaborate on in this patch: https://lore.kernel.org/r/20250615045145.224567-1-ebiggers@kernel.org - Eric _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv