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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4538233c05csm24091875e9.5.2025.06.25.09.02.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jun 2025 09:02:48 -0700 (PDT) Date: Wed, 25 Jun 2025 17:02:34 +0100 From: David Laight To: Yury Norov Cc: cp0613@linux.alibaba.com, linux@rasmusvillemoes.dk, arnd@arndb.de, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] bitops: rotate: Add riscv implementation using Zbb extension Message-ID: <20250625170234.29605eed@pumpkin> In-Reply-To: References: <20250620111610.52750-1-cp0613@linux.alibaba.com> <20250620111610.52750-3-cp0613@linux.alibaba.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250625_090251_032641_43884D9C X-CRM114-Status: GOOD ( 19.31 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, 20 Jun 2025 12:20:47 -0400 Yury Norov wrote: > On Fri, Jun 20, 2025 at 07:16:10PM +0800, cp0613@linux.alibaba.com wrote: > > From: Chen Pei > > > > The RISC-V Zbb extension[1] defines bitwise rotation instructions, > > which can be used to implement rotate related functions. > > > > [1] https://github.com/riscv/riscv-bitmanip/ > > > > Signed-off-by: Chen Pei > > --- > > arch/riscv/include/asm/bitops.h | 172 ++++++++++++++++++++++++++++++++ > > 1 file changed, 172 insertions(+) > > > > diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h > > index d59310f74c2b..be247ef9e686 100644 > > --- a/arch/riscv/include/asm/bitops.h > > +++ b/arch/riscv/include/asm/bitops.h > > @@ -20,17 +20,20 @@ > > #include > > #include > > #include > > +#include > > > > #else > > #define __HAVE_ARCH___FFS > > #define __HAVE_ARCH___FLS > > #define __HAVE_ARCH_FFS > > #define __HAVE_ARCH_FLS > > +#define __HAVE_ARCH_ROTATE > > > > #include > > #include > > #include > > #include > > +#include > > > > #include > > #include > > @@ -175,6 +178,175 @@ static __always_inline int variable_fls(unsigned int x) > > variable_fls(x_); \ > > }) > > ... > > > +static inline u8 variable_ror8(u8 word, unsigned int shift) > > +{ > > + u32 word32 = ((u32)word << 24) | ((u32)word << 16) | ((u32)word << 8) | word; > > Can you add a comment about what is happening here? Are you sure it's > optimized out in case of the 'legacy' alternative? Is it even a gain in the zbb case? The "rorw" is only ever going to help full word rotates. Here you might as well do ((word << 8 | word) >> shift). For "rol8" you'd need ((word << 24 | word) 'rol' shift). I still bet the generic code is faster (but see below). Same for 16bit rotates. Actually the generic version is (probably) horrid for everything except x86. See https://www.godbolt.org/z/xTxYj57To unsigned char rol(unsigned char v, unsigned int shift) { return (v << 8 | v) << shift >> 8; } unsigned char ror(unsigned char v, unsigned int shift) { return (v << 8 | v) >> shift; } David _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv