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Thu, 26 Jun 2025 02:21:12 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::5485]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4538a3fe587sm13667895e9.19.2025.06.26.02.21.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jun 2025 02:21:11 -0700 (PDT) Date: Thu, 26 Jun 2025 11:21:10 +0200 From: Andrew Jones To: Aleksa Paunovic via B4 Relay Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic Subject: Re: [PATCH v4 6/7] riscv: Add tools support for xmipsexectl Message-ID: <20250626-a1aca9887bbf5410741e17c4@orel> References: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> <20250625-p8700-pause-v4-6-6c7dd7f85756@htecgroup.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250625-p8700-pause-v4-6-6c7dd7f85756@htecgroup.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250626_022114_246946_429601ED X-CRM114-Status: GOOD ( 22.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Jun 25, 2025 at 04:21:01PM +0200, Aleksa Paunovic via B4 Relay wrote: > From: Aleksa Paunovic > > Use the hwprobe syscall to decide which PAUSE instruction to execute in > userspace code. > > Signed-off-by: Aleksa Paunovic > --- > tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++---------- > 1 file changed, 17 insertions(+), 10 deletions(-) > > diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h > index 662aca03984817f9c69186658b19e9dad9e4771c..027219a486b7b93814888190f8224af29498707c 100644 > --- a/tools/arch/riscv/include/asm/vdso/processor.h > +++ b/tools/arch/riscv/include/asm/vdso/processor.h > @@ -4,26 +4,33 @@ > > #ifndef __ASSEMBLY__ > > +#include > +#include > +#include > #include > > static inline void cpu_relax(void) > { > + struct riscv_hwprobe pair; > + bool has_mipspause; > #ifdef __riscv_muldiv > int dummy; > /* In lieu of a halt instruction, induce a long-latency stall. */ > __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > #endif > > -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE > - /* > - * Reduce instruction retirement. > - * This assumes the PC changes. > - */ > - __asm__ __volatile__ ("pause"); > -#else > - /* Encoding of the pause instruction */ > - __asm__ __volatile__ (".4byte 0x100000F"); > -#endif > + pair.key = RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0; > + __riscv_hwprobe(&pair, 1, 0, NULL, 0); > + has_mipspause = pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL; > + > + if (has_mipspause) { > + /* Encoding of the mips pause instruction */ > + __asm__ __volatile__(".4byte 0x00501013"); > + } else { > + /* Encoding of the pause instruction */ > + __asm__ __volatile__(".4byte 0x100000F"); > + } > + cpu_relax() is used in places where we cannot afford the overhead nor call arbitrary functions which may take locks, etc. We've even had trouble using a static key here in the past since this is inlined and it bloated the size too much. You'll need to use ALTERNATIVE(). Thanks, drew > barrier(); > } > > > -- > 2.34.1 > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv