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[2003:e4:1f4e:9b00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3b5e8bd15bfsm20610595f8f.19.2025.07.17.03.32.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jul 2025 03:32:50 -0700 (PDT) From: Thierry Reding To: Greg Kroah-Hartman Cc: x86@kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-mips@vger.kernel.org, loongarch@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/7] MIPS: Embed syscore_ops in PCI context Date: Thu, 17 Jul 2025 12:32:36 +0200 Message-ID: <20250717103241.2806798-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250717103241.2806798-1-thierry.reding@gmail.com> References: <20250717103241.2806798-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250717_033254_130694_4EE2593F X-CRM114-Status: GOOD ( 14.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Thierry Reding This enables the syscore callbacks to obtain the PCI context without relying on a separate global variable. Signed-off-by: Thierry Reding --- arch/mips/pci/pci-alchemy.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c index a20de7160b6b..02f0616518e1 100644 --- a/arch/mips/pci/pci-alchemy.c +++ b/arch/mips/pci/pci-alchemy.c @@ -33,6 +33,7 @@ struct alchemy_pci_context { struct pci_controller alchemy_pci_ctrl; /* leave as first member! */ + struct syscore_ops pmops; void __iomem *regs; /* ctrl base */ /* tools for wired entry for config space access */ unsigned long last_elo0; @@ -46,6 +47,12 @@ struct alchemy_pci_context { int (*board_pci_idsel)(unsigned int devsel, int assert); }; +static inline struct alchemy_pci_context * +syscore_to_pci_context(struct syscore_ops *ops) +{ + return container_of(ops, struct alchemy_pci_context, pmops); +} + /* for syscore_ops. There's only one PCI controller on Alchemy chips, so this * should suffice for now. */ @@ -306,9 +313,7 @@ static int alchemy_pci_def_idsel(unsigned int devsel, int assert) /* save PCI controller register contents. */ static int alchemy_pci_suspend(struct syscore_ops *ops) { - struct alchemy_pci_context *ctx = __alchemy_pci_ctx; - if (!ctx) - return 0; + struct alchemy_pci_context *ctx = syscore_to_pci_context(ops); ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; @@ -328,9 +333,7 @@ static int alchemy_pci_suspend(struct syscore_ops *ops) static void alchemy_pci_resume(struct syscore_ops *ops) { - struct alchemy_pci_context *ctx = __alchemy_pci_ctx; - if (!ctx) - return; + struct alchemy_pci_context *ctx = syscore_to_pci_context(ops); __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); @@ -354,11 +357,6 @@ static void alchemy_pci_resume(struct syscore_ops *ops) alchemy_pci_wired_entry(ctx); /* install it */ } -static struct syscore_ops alchemy_pci_pmops = { - .suspend = alchemy_pci_suspend, - .resume = alchemy_pci_resume, -}; - static int alchemy_pci_probe(struct platform_device *pdev) { struct alchemy_pci_platdata *pd = pdev->dev.platform_data; @@ -478,7 +476,9 @@ static int alchemy_pci_probe(struct platform_device *pdev) __alchemy_pci_ctx = ctx; platform_set_drvdata(pdev, ctx); - register_syscore_ops(&alchemy_pci_pmops); + ctx->pmops.suspend = alchemy_pci_suspend; + ctx->pmops.resume = alchemy_pci_resume; + register_syscore_ops(&ctx->pmops); register_pci_controller(&ctx->alchemy_pci_ctrl); dev_info(&pdev->dev, "PCI controller at %ld MHz\n", -- 2.50.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv