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From: Junhui Liu <junhui.liu@pigmoral.tech>
To: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Alexandre Ghiti <alex@ghiti.fr>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	 Thomas Gleixner <tglx@linutronix.de>,
	 Samuel Holland <samuel.holland@sifive.com>,
	 Anup Patel <anup@brainfault.org>,
	 Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	 Jiri Slaby <jirislaby@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Palmer Dabbelt <palmer@sifive.com>,
	Conor Dooley <conor@kernel.org>,
	 linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
	 Junhui Liu <junhui.liu@pigmoral.tech>
Subject: [PATCH RFC 02/10] dt-bindings: riscv: Add Nuclei UX900 compatibles
Date: Mon, 21 Jul 2025 23:46:08 +0800	[thread overview]
Message-ID: <20250721-dr1v90-basic-dt-v1-2-5740c5199c47@pigmoral.tech> (raw)
In-Reply-To: <20250721-dr1v90-basic-dt-v1-0-5740c5199c47@pigmoral.tech>

The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC.
It features a 64-bit architecture and dual-issue, 9-stage pipeline, with
lots of optional extensions including V, K, Zc, and more.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 2c72f148a74b019e46ad5917a0b75d45777c385e..f198d8b1fa328f538b4a2983ca795340337fbd2b 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
               - amd,mbv32
               - andestech,ax45mp
               - canaan,k210
+              - nuclei,ux900
               - sifive,bullet0
               - sifive,e5
               - sifive,e7

-- 
2.50.1


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  parent reply	other threads:[~2025-07-21 16:55 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-21 15:46 [PATCH RFC 00/10] riscv: Add initial support for Anlogic DR1V90 Junhui Liu
2025-07-21 15:46 ` [PATCH RFC 01/10] dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei Junhui Liu
2025-07-22  7:27   ` Krzysztof Kozlowski
2025-07-21 15:46 ` Junhui Liu [this message]
2025-07-21 15:46 ` [PATCH RFC 03/10] dt-bindings: riscv: Add Anlogic DR1V90 Junhui Liu
2025-07-22  7:28   ` Krzysztof Kozlowski
2025-07-21 15:46 ` [PATCH RFC 04/10] dt-bindings: timer: Add Anlogic DR1V90 CLINT Junhui Liu
2025-07-25 22:29   ` Rob Herring (Arm)
2025-07-21 15:46 ` [PATCH RFC 05/10] dt-bindings: interrupt-controller: Add Anlogic DR1V90 PLIC Junhui Liu
2025-07-21 15:46 ` [PATCH RFC 06/10] dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart Junhui Liu
2025-07-25 22:30   ` Rob Herring (Arm)
2025-07-21 15:46 ` [PATCH RFC 07/10] riscv: Add Anlogic SoC famly Kconfig support Junhui Liu
2025-07-22  7:29   ` Krzysztof Kozlowski
2025-07-22 11:27     ` Junhui Liu
2025-07-21 15:46 ` [PATCH RFC 08/10] riscv: dts: Add initial Anlogic DR1V90 SoC device tree Junhui Liu
2025-07-22 15:21   ` Conor Dooley
2025-07-23  2:37     ` Junhui Liu
2025-07-21 15:46 ` [PATCH RFC 09/10] riscv: dts: anlogic: Add Milianke MLKPAI FS01 board Junhui Liu
2025-07-22  7:31   ` Krzysztof Kozlowski
2025-07-22 11:46     ` Junhui Liu
2025-07-21 15:46 ` [PATCH RFC 10/10] riscv: defconfig: Enable Anlogic SoC Junhui Liu

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