[PATCH v2 0/2] riscv-imsic/aplic: Save and restore the registers

From: Nick Hu <nick.hu@sifive.com>
To: anup@brainfault.org, Alexandre Ghiti <alex@ghiti.fr>,
	linux-riscv@lists.infradead.org
Cc: Nick Hu <nick.hu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Subject: [PATCH v2 0/2] riscv-imsic/aplic: Save and restore the registers
Date: Wed,  6 Aug 2025 16:27:24 +0800	[thread overview]
Message-ID: <20250806082726.8835-1-nick.hu@sifive.com> (raw)

Since the APLIC and IMSIC may be powered down when the CPUs enter a deep
sleep state, it is necessary to implement save and restore functions to
ensure their states are correctly preserved and restored.

Changes in V2:
- Address the compile error from kernel test robot when
  CONFIG_RISCV_M_MODE is enabled.
- Apply the suggestion from Anup [1]

Link:
- [1] https://lore.kernel.org/linux-riscv/20250709025516.28051-1-nick.hu@sifive.com/

Nick Hu (2):
  irqchip/riscv-imsic: Restore the IMSIC registers
  irqchip/riscv-aplic: Save and restore APLIC registers

 drivers/irqchip/irq-riscv-aplic-direct.c |  11 ++
 drivers/irqchip/irq-riscv-aplic-main.c   | 158 ++++++++++++++++++++++-
 drivers/irqchip/irq-riscv-aplic-main.h   |  11 ++
 drivers/irqchip/irq-riscv-imsic-early.c  |  41 ++++--
 4 files changed, 212 insertions(+), 9 deletions(-)

-- 
2.17.1

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