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McKenney" , Boqun Feng , Quan Zhou Subject: Re: [PATCH v2 3/3] KVM: riscv: selftests: Add missing headers for new testcases Message-ID: <20250818-4672b703d0bf9518ee1d4162@orel> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250818_140118_638995_28390BCF X-CRM114-Status: GOOD ( 17.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Aug 07, 2025 at 10:59:30PM +0800, dayss1224@gmail.com wrote: > From: Dong Yang > > Add missing headers to fix the build for new RISC-V KVM selftests. > > Signed-off-by: Quan Zhou > Signed-off-by: Dong Yang > --- > tools/testing/selftests/kvm/include/riscv/processor.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h > index 162f303d9..4cf5ae117 100644 > --- a/tools/testing/selftests/kvm/include/riscv/processor.h > +++ b/tools/testing/selftests/kvm/include/riscv/processor.h > @@ -9,7 +9,9 @@ > > #include > #include > +#include This is fine, but... > #include "kvm_util.h" > +#include "ucall_common.h" ...this isn't correct. We should instead add this include line to all the source files that need it: access_tracking_perf_test.c memslot_modification_stress_test.c memslot_perf_test.c Thanks, drew > > #define INSN_OPCODE_MASK 0x007c > #define INSN_OPCODE_SHIFT 2 > -- > 2.34.1 > > > -- > kvm-riscv mailing list > kvm-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/kvm-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv