From: Andrew Jones <ajones@ventanamicro.com>
To: Jimmy Ho <jimmy.ho@sifive.com>
Cc: linux-riscv@lists.infradead.org,
troy.mitchell@linux.spacemit.com, ziyao@disroot.org,
paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, cyrilbur@tenstorrent.com,
cleger@rivosinc.com, charlie@rivosinc.com, kees@kernel.org,
ben.dooks@codethink.co.uk, jszhang@kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3] riscv: fix using wrong load type
Date: Tue, 19 Aug 2025 13:23:32 -0500 [thread overview]
Message-ID: <20250819-cf406b3d02087824245b5576@orel> (raw)
In-Reply-To: <20250819071318.21103-1-jimmy.ho@sifive.com>
On Tue, Aug 19, 2025 at 03:13:18PM +0800, Jimmy Ho wrote:
> thread_info.cpu field is 32 bits wide,
> but is accessed using an XLEN-bit load, which might be 64bit load, fix it
>
> Changes in v3:
> - replace space with tab to keep it aligned with code block
> - Add "Fixes" tag
>
> Changes in v2:
> - add a comment to explain why use lw instead of REG_L.
> - correct commit message
The changelog belongs below the --- in the patch.
>
> Fixes: 503638e0babf3 ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings")
> Signed-off-by: Jimmy Ho <jimmy.ho@sifive.com>
> ---
> arch/riscv/kernel/entry.S | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 3a0ec6fd5956..492ae936dccd 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -45,8 +45,10 @@
> * Computes:
> * a0 = &new_vmalloc[BIT_WORD(cpu)]
> * a1 = BIT_MASK(cpu)
> + *
> + * using lw instead of REG_L is because the thread_info.cpu field is 32 bits wide
> */
> - REG_L a2, TASK_TI_CPU(tp)
> + lw a2, TASK_TI_CPU(tp)
> /*
> * Compute the new_vmalloc element position:
> * (cpu / 64) * 8 = (cpu >> 6) << 3
> --
> 2.39.3
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
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prev parent reply other threads:[~2025-08-19 20:42 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-19 7:13 [PATCH v3] riscv: fix using wrong load type Jimmy Ho
2025-08-19 7:19 ` Troy Mitchell
2025-08-19 7:20 ` Troy Mitchell
2025-08-19 18:25 ` Andrew Jones
2025-08-19 18:23 ` Andrew Jones [this message]
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