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Tue, 19 Aug 2025 11:23:33 -0700 (PDT) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-8843f7f9854sm411794739f.7.2025.08.19.11.23.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 11:23:32 -0700 (PDT) Date: Tue, 19 Aug 2025 13:23:32 -0500 From: Andrew Jones To: Jimmy Ho Cc: linux-riscv@lists.infradead.org, troy.mitchell@linux.spacemit.com, ziyao@disroot.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, cyrilbur@tenstorrent.com, cleger@rivosinc.com, charlie@rivosinc.com, kees@kernel.org, ben.dooks@codethink.co.uk, jszhang@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] riscv: fix using wrong load type Message-ID: <20250819-cf406b3d02087824245b5576@orel> References: <20250819071318.21103-1-jimmy.ho@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250819071318.21103-1-jimmy.ho@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250819_112334_192142_B0B545E1 X-CRM114-Status: GOOD ( 19.16 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Aug 19, 2025 at 03:13:18PM +0800, Jimmy Ho wrote: > thread_info.cpu field is 32 bits wide, > but is accessed using an XLEN-bit load, which might be 64bit load, fix it > > Changes in v3: > - replace space with tab to keep it aligned with code block > - Add "Fixes" tag > > Changes in v2: > - add a comment to explain why use lw instead of REG_L. > - correct commit message The changelog belongs below the --- in the patch. > > Fixes: 503638e0babf3 ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") > Signed-off-by: Jimmy Ho > --- > arch/riscv/kernel/entry.S | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > index 3a0ec6fd5956..492ae936dccd 100644 > --- a/arch/riscv/kernel/entry.S > +++ b/arch/riscv/kernel/entry.S > @@ -45,8 +45,10 @@ > * Computes: > * a0 = &new_vmalloc[BIT_WORD(cpu)] > * a1 = BIT_MASK(cpu) > + * > + * using lw instead of REG_L is because the thread_info.cpu field is 32 bits wide > */ > - REG_L a2, TASK_TI_CPU(tp) > + lw a2, TASK_TI_CPU(tp) > /* > * Compute the new_vmalloc element position: > * (cpu / 64) * 8 = (cpu >> 6) << 3 > -- > 2.39.3 Otherwise, Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv