From: Ben Dooks <ben.dooks@codethink.co.uk>
To: linux-riscv@lists.infradead.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: -linux-kernel@vger.kernel.org, Alexandre Ghiti <alex@ghiti.fr>,
Javier Jardon <javier.jardon@codethink.co.uk>,
Ben Dooks <bjdooks@gmail.com>,
Lawrence Hunter <lawrence.hunter@codethink.co.uk>,
Roan Richmod <roan.richmond@codethink.co.uk>,
Sam Grove <sgrove@mips.com>, Chao-ying Fu <cfu@mips.com>,
Mukunda Aprameya <maprameya@mips.com>,
Umesh Kalappa <ukalappa@mips.com>,
Djordje Todorovic <djordje.todorovic@htecgroup.com>,
Kurt Martin <kmartin@mips.com>,
allikarjuna Gouda <mgouda@mips.com>,
Vaibhav Chauthmal <vchauthmal@mips.com>,
wapnil Agrawal <sagrawal@mips.com>,
Ben Dooks <ben.dooks@codethink.co.uk>
Subject: [PATCH 13/18] riscv: fixes for big-endian library routines
Date: Fri, 22 Aug 2025 17:52:43 +0100 [thread overview]
Message-ID: <20250822165248.289802-14-ben.dooks@codethink.co.uk> (raw)
In-Reply-To: <20250822165248.289802-1-ben.dooks@codethink.co.uk>
Update the unaligned handling of memory when in big-endian
and the byte positions inside a loaded word change. Do this
by wrapping the shift macros and swapping the left and right
shfits.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
arch/riscv/lib/memmove.S | 28 ++++++++++++++++++++--------
arch/riscv/lib/uaccess.S | 16 ++++++++++++++--
2 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S
index cb3e2e7ef0ba..6971006a8eb6 100644
--- a/arch/riscv/lib/memmove.S
+++ b/arch/riscv/lib/memmove.S
@@ -6,6 +6,18 @@
#include <linux/linkage.h>
#include <asm/asm.h>
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#define M_SLL sll
+#define M_SRL srl
+#else
+ /* in big-endian, swap the direction of shifts to deal
+ * with the fact the order of bytes in a word has changed
+ * from ABCD to DCBA.
+ */
+#define M_SLL srl
+#define M_SRL sll
+#endif
+
SYM_FUNC_START(__memmove)
/*
* Returns
@@ -133,8 +145,8 @@ SYM_FUNC_START(__memmove)
1:
REG_L t1, (1 * SZREG)(a1)
addi t3, t3, (2 * SZREG)
- srl t0, t0, a6
- sll t2, t1, a7
+ M_SRL t0, t0, a6
+ M_SLL t2, t1, a7
or t2, t0, t2
REG_S t2, ((0 * SZREG) - (2 * SZREG))(t3)
@@ -142,8 +154,8 @@ SYM_FUNC_START(__memmove)
REG_L t0, (2 * SZREG)(a1)
addi a1, a1, (2 * SZREG)
- srl t1, t1, a6
- sll t2, t0, a7
+ M_SRL t1, t1, a6
+ M_SLL t2, t0, a7
or t2, t1, t2
REG_S t2, ((1 * SZREG) - (2 * SZREG))(t3)
@@ -195,8 +207,8 @@ SYM_FUNC_START(__memmove)
1:
REG_L t0, (-1 * SZREG)(a4)
addi t4, t4, (-2 * SZREG)
- sll t1, t1, a7
- srl t2, t0, a6
+ M_SLL t1, t1, a7
+ M_SRL t2, t0, a6
or t2, t1, t2
REG_S t2, ( 1 * SZREG)(t4)
@@ -204,8 +216,8 @@ SYM_FUNC_START(__memmove)
REG_L t1, (-2 * SZREG)(a4)
addi a4, a4, (-2 * SZREG)
- sll t0, t0, a7
- srl t2, t1, a6
+ M_SLL t0, t0, a7
+ M_SRL t2, t1, a6
or t2, t0, t2
REG_S t2, ( 0 * SZREG)(t4)
diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
index 4efea1b3326c..71ee4811db68 100644
--- a/arch/riscv/lib/uaccess.S
+++ b/arch/riscv/lib/uaccess.S
@@ -6,6 +6,18 @@
#include <asm/hwcap.h>
#include <asm/alternative-macros.h>
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#define M_SLL sll
+#define M_SRL srl
+#else
+ /* in big-endian, swap the direction of shifts to deal
+ * with the fact the order of bytes in a word has changed
+ * from ABCD to DCBA.
+ */
+#define M_SLL srl
+#define M_SRL sll
+#endif
+
.macro fixup op reg addr lbl
100:
\op \reg, \addr
@@ -178,10 +190,10 @@ SYM_FUNC_START(fallback_scalar_usercopy_sum_enabled)
*/
/* At least one iteration will be executed */
- srl a4, a5, t3
+ M_SRL a4, a5, t3
fixup REG_L a5, SZREG(a1), 10f
addi a1, a1, SZREG
- sll a2, a5, t4
+ M_SLL a2, a5, t4
or a2, a2, a4
fixup REG_S a2, 0(a0), 10f
addi a0, a0, SZREG
--
2.37.2.352.g3c44437643
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next prev parent reply other threads:[~2025-08-23 9:36 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-22 16:52 RISC-V big-endian support Ben Dooks
2025-08-22 16:52 ` [PATCH 01/18] riscv: add initial kconfig and build flags for big-endian Ben Dooks
2025-08-22 16:52 ` [PATCH 02/18] riscv: update byteorder.h " Ben Dooks
2025-08-22 16:52 ` [PATCH 03/18] riscv: disable vector if big-endian, gcc unsupported option Ben Dooks
2025-08-22 16:52 ` [PATCH 04/18] riscv: word-at-atime: move to generic if we're big endian Ben Dooks
2025-08-22 16:52 ` [PATCH 05/18] riscv: asm: use .insn for making custom instructioons Ben Dooks
2025-08-22 16:52 ` [PATCH 06/18] kconfig: remove CONFIG_COMAPT for big-endian Ben Dooks
2025-08-22 16:52 ` [PATCH 07/18] riscv: fixup use of natural endian on instructions Ben Dooks
2025-08-22 16:52 ` [PATCH 08/18] riscv: bpf: big endian fixes, updated BPF_ALU ops Ben Dooks
2025-08-22 16:52 ` [PATCH 09/18] riscv: probes: sort out endian-ness Ben Dooks
2025-08-22 16:52 ` [PATCH 10/18] riscv: ftrace big endian updates Ben Dooks
2025-08-22 16:52 ` [PATCH 11/18] riscv: traps: make insn fetch common in unknown instruction Ben Dooks
2025-08-22 16:52 ` [PATCH 12/18] riscv: threads need UBE flag setting if big-endian Ben Dooks
2025-08-22 16:52 ` Ben Dooks [this message]
2025-08-22 16:52 ` [PATCH 14/18] riscv: update to add ASM_INSN for .2byte instructions Ben Dooks
2025-08-22 16:52 ` [PATCH 15/18] KVM: riscv: set HSTATUS big endian same as build Ben Dooks
2025-08-22 16:52 ` [PATCH 16/18] KVM: riscv: add hstatus to allow endian control Ben Dooks
2025-08-22 16:52 ` [PATCH 17/18] KVM: riscv: instructions are little endian Ben Dooks
2025-08-22 16:52 ` [PATCH 18/18] KVM: riscv: add warning if undecoded instruction Ben Dooks
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