* [PATCH v3 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110
@ 2025-08-23 8:57 E Shattow
2025-08-23 8:58 ` [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller E Shattow
2025-08-23 8:58 ` [PATCH v3 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader E Shattow
0 siblings, 2 replies; 5+ messages in thread
From: E Shattow @ 2025-08-23 8:57 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: devicetree, linux-kernel, Hal Feng, Minda Chen, E Shattow,
linux-riscv
Bring in additional downstream U-Boot boot loader changes for StarFive
VisionFive2 board target (and related JH7110 common boards). Create a
basic dt-binding (and not any Linux driver) in support of the
memory-controller dts node used in mainline U-Boot. Also add
bootph-pre-ram hinting to jh7110.dtsi needed at SPL boot phase.
Changes since v2:
- patch 1/3 "add StarFive JH7110 SoC DMC": wrap at 80 col, clock-names
const is 'pll'.
- patch 2/3 "add memory controller node": memory-controller node follows
sorting style by reg address, between watchdog and crypto nodes. Update
clock-names to 'pll'.
- patch 3/3 "bootph-pre-ram hinting needed by boot loader": add missing
hints for syscrg dependencies 'gmac1_rgmii_rxin', 'gmac1_rmii_refin',
and 'pllclk'.
E Shattow (3):
dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
riscv: dts: starfive: jh7110: add DMC memory controller
riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
loader
.../starfive,jh7110-dmc.yaml | 74 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 24 ++++++
2 files changed, 98 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
base-commit: 481ee0fcbb9a0f0706d6d29de9570d1048aff631
--
2.50.0
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller 2025-08-23 8:57 [PATCH v3 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow @ 2025-08-23 8:58 ` E Shattow 2025-08-23 8:58 ` [PATCH v3 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader E Shattow 1 sibling, 0 replies; 5+ messages in thread From: E Shattow @ 2025-08-23 8:58 UTC (permalink / raw) To: Emil Renner Berthing, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Cc: devicetree, linux-kernel, Hal Feng, Minda Chen, E Shattow, linux-riscv Add JH7110 SoC DDR external memory controller. Signed-off-by: E Shattow <e@freeshell.de> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 0ba74ef04679..f3876660c07f 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -931,6 +931,18 @@ watchdog@13070000 { <&syscrg JH7110_SYSRST_WDT_CORE>; }; + memory-controller@15700000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll"; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + }; + crypto: crypto@16000000 { compatible = "starfive,jh7110-crypto"; reg = <0x0 0x16000000 0x0 0x4000>; -- 2.50.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader 2025-08-23 8:57 [PATCH v3 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow 2025-08-23 8:58 ` [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller E Shattow @ 2025-08-23 8:58 ` E Shattow 1 sibling, 0 replies; 5+ messages in thread From: E Shattow @ 2025-08-23 8:58 UTC (permalink / raw) To: Emil Renner Berthing, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Cc: devicetree, linux-kernel, Hal Feng, Minda Chen, E Shattow, linux-riscv Add bootph-pre-ram hinting to jh7110.dtsi: - CPU interrupt controller(s) - gmac1_rgmii_rxin fixed-clock (dependency of syscrg) - gmac1_rmii_refin fixed-clock (dependency of syscrg) - oscillator - core local interrupt timer - syscrg clock-controller - pllclk clock-controller (dependency of syscrg) - DDR memory controller Signed-off-by: E Shattow <e@freeshell.de> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index f3876660c07f..6e56e9d20bb0 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -35,6 +35,7 @@ S7_0: cpu@0 { cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells = <1>; }; @@ -68,6 +69,7 @@ U74_1: cpu@1 { cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells = <1>; }; @@ -101,6 +103,7 @@ U74_2: cpu@2 { cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells = <1>; }; @@ -134,6 +137,7 @@ U74_3: cpu@3 { cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells = <1>; }; @@ -167,6 +171,7 @@ U74_4: cpu@4 { cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells = <1>; }; @@ -273,12 +278,14 @@ gmac0_rmii_refin: gmac0-rmii-refin-clock { gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { compatible = "fixed-clock"; + bootph-pre-ram; clock-output-names = "gmac1_rgmii_rxin"; #clock-cells = <0>; }; gmac1_rmii_refin: gmac1-rmii-refin-clock { compatible = "fixed-clock"; + bootph-pre-ram; clock-output-names = "gmac1_rmii_refin"; #clock-cells = <0>; }; @@ -321,6 +328,7 @@ mclk_ext: mclk-ext-clock { osc: oscillator { compatible = "fixed-clock"; + bootph-pre-ram; clock-output-names = "osc"; #clock-cells = <0>; }; @@ -354,6 +362,7 @@ soc { clint: timer@2000000 { compatible = "starfive,jh7110-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0x10000>; + bootph-pre-ram; interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, <&cpu1_intc 7>, <&cpu2_intc 3>, <&cpu2_intc 7>, @@ -880,6 +889,7 @@ qspi: spi@13010000 { syscrg: clock-controller@13020000 { compatible = "starfive,jh7110-syscrg"; reg = <0x0 0x13020000 0x0 0x10000>; + bootph-pre-ram; clocks = <&osc>, <&gmac1_rmii_refin>, <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, @@ -904,6 +914,7 @@ sys_syscon: syscon@13030000 { pllclk: clock-controller { compatible = "starfive,jh7110-pll"; + bootph-pre-ram; clocks = <&osc>; #clock-cells = <1>; }; @@ -935,6 +946,7 @@ memory-controller@15700000 { compatible = "starfive,jh7110-dmc"; reg = <0x0 0x15700000 0x0 0x10000>, <0x0 0x13000000 0x0 0x10000>; + bootph-pre-ram; clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; clock-names = "pll"; resets = <&syscrg JH7110_SYSRST_DDR_AXI>, -- 2.50.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 RESEND 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110
@ 2025-08-23 10:01 E Shattow
2025-08-23 10:01 ` [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller E Shattow
0 siblings, 1 reply; 5+ messages in thread
From: E Shattow @ 2025-08-23 10:01 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: linux-riscv, devicetree, linux-kernel, Hal Feng, Minda Chen,
E Shattow
Bring in additional downstream U-Boot boot loader changes for StarFive
VisionFive2 board target (and related JH7110 common boards). Create a
basic dt-binding (and not any Linux driver) in support of the
memory-controller dts node used in mainline U-Boot. Also add
bootph-pre-ram hinting to jh7110.dtsi needed at SPL boot phase.
Changes since v2:
- patch 1/3 "add StarFive JH7110 SoC DMC": wrap at 80 col, clock-names
const is 'pll'.
- patch 2/3 "add memory controller node": memory-controller node follows
sorting style by reg address, between watchdog and crypto nodes. Update
clock-names to 'pll'.
- patch 3/3 "bootph-pre-ram hinting needed by boot loader": add missing
hints for syscrg dependencies 'gmac1_rgmii_rxin', 'gmac1_rmii_refin',
and 'pllclk'.
E Shattow (3):
dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
riscv: dts: starfive: jh7110: add DMC memory controller
riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
loader
.../starfive,jh7110-dmc.yaml | 74 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 24 ++++++
2 files changed, 98 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
base-commit: 481ee0fcbb9a0f0706d6d29de9570d1048aff631
--
2.50.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller 2025-08-23 10:01 [PATCH v3 RESEND 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow @ 2025-08-23 10:01 ` E Shattow 2025-08-23 17:34 ` Hal Feng 0 siblings, 1 reply; 5+ messages in thread From: E Shattow @ 2025-08-23 10:01 UTC (permalink / raw) To: Emil Renner Berthing, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Cc: linux-riscv, devicetree, linux-kernel, Hal Feng, Minda Chen, E Shattow Add JH7110 SoC DDR external memory controller. Signed-off-by: E Shattow <e@freeshell.de> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 0ba74ef04679..f3876660c07f 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -931,6 +931,18 @@ watchdog@13070000 { <&syscrg JH7110_SYSRST_WDT_CORE>; }; + memory-controller@15700000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll"; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + }; + crypto: crypto@16000000 { compatible = "starfive,jh7110-crypto"; reg = <0x0 0x16000000 0x0 0x4000>; -- 2.50.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller 2025-08-23 10:01 ` [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller E Shattow @ 2025-08-23 17:34 ` Hal Feng 0 siblings, 0 replies; 5+ messages in thread From: Hal Feng @ 2025-08-23 17:34 UTC (permalink / raw) To: E Shattow, Emil Renner Berthing, Conor Dooley, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org > On 23.08.25 18:02, E Shattow wrote: > > Add JH7110 SoC DDR external memory controller. > > Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Best regards, Hal > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi > b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 0ba74ef04679..f3876660c07f 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -931,6 +931,18 @@ watchdog@13070000 { > <&syscrg JH7110_SYSRST_WDT_CORE>; > }; > > + memory-controller@15700000 { > + compatible = "starfive,jh7110-dmc"; > + reg = <0x0 0x15700000 0x0 0x10000>, > + <0x0 0x13000000 0x0 0x10000>; > + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; > + clock-names = "pll"; > + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, > + <&syscrg JH7110_SYSRST_DDR_OSC>, > + <&syscrg JH7110_SYSRST_DDR_APB>; > + reset-names = "axi", "osc", "apb"; > + }; > + > crypto: crypto@16000000 { > compatible = "starfive,jh7110-crypto"; > reg = <0x0 0x16000000 0x0 0x4000>; > -- > 2.50.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-08-23 19:09 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-08-23 8:57 [PATCH v3 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow 2025-08-23 8:58 ` [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller E Shattow 2025-08-23 8:58 ` [PATCH v3 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader E Shattow -- strict thread matches above, loose matches on Subject: below -- 2025-08-23 10:01 [PATCH v3 RESEND 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow 2025-08-23 10:01 ` [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller E Shattow 2025-08-23 17:34 ` Hal Feng
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