From: Conor Dooley <conor@kernel.org>
To: Drew Fustini <fustini@kernel.org>
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Kornel Dulęba" <mindal@semihalf.com>,
"Adrien Ricciardi" <aricciardi@baylibre.com>,
"James Morse" <james.morse@arm.com>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Atish Patra" <atish.patra@linux.dev>,
"Vasudevan Srinivasan" <vasu@rivosinc.com>,
guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/2] RISC-V: Detect Ssqosid extension and handle srmcfg CSR
Date: Thu, 11 Sep 2025 17:23:30 +0100 [thread overview]
Message-ID: <20250911-chaste-rare-fbc3b48a341a@spud> (raw)
In-Reply-To: <20250910-ssqosid-v6-17-rc5-v1-0-72cb8f144615@kernel.org>
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On Wed, Sep 10, 2025 at 11:15:28PM -0700, Drew Fustini wrote:
> This series adds support for the RISC-V Quality-of-Service Identifiers
> (Ssqosid) extension [1] which adds the srmcfg register. This CSR
> configures a hart with two identifiers: a Resource Control ID (RCID)
> and a Monitoring Counter ID (MCID). These identifiers accompany each
> request issued by the hart to shared resource controllers.
>
> Background on RISC-V QoS:
>
> The Ssqosid extension is used by the RISC-V Capacity and Bandwidth
> Controller QoS Register Interface (CBQRI) specification [2]. QoS in
> this context is concerned with shared resources on an SoC such as cache
> capacity and memory bandwidth. Intel and AMD already have QoS features
> on x86 and ARM has MPAM. There is an existing user interface in Linux:
> the resctrl virtual filesystem [3].
>
> The srmcfg CSR provides a mechanism by which a software workload (e.g.
> a process or a set of processes) can be associated with an RCID and an
> MCID. CBQRI defines operations to configure resource usage limits, in
> the form of capacity or bandwidth. CBQRI also defines operations to
> configure counters to track the resource utilization.
>
> Goal for this series:
>
> These two patches are taken from the implementation of resctrl support
> for RISC-V CBQRI. Please refer to the proof-of-concept RFC [4] for
> details on the resctrl implementation. More recently, I have rebased
> the CBQRI support on mainline [5]. Big thanks to James Morse for the
> tireless work to extract resctrl from arch/x86 and make it available
> to all archs.
>
> I think it makes sense to first focus on the detection of Ssqosid and
> handling of srmcfg when switching tasks. It has been tested against a
> QEMU branch that implements Ssqosid and CBQRI [6]. A test driver [7]
> was used to set srmcfg for the current process. This allows switch_to
> to be tested without resctrl.
>
> Changes from RFC v2:
> - Rename all instances of the sqoscfg CSR to srmcfg to match the
> ratified Ssqosid spec
> - RFC v2: https://lore.kernel.org/linux-riscv/20230430-riscv-cbqri-rfc-v2-v2-0-8e3725c4a473@baylibre.com/
>
> Changes from RFC v1:
> - change DEFINE_PER_CPU to DECLARE_PER_CPU for cpu_sqoscfg in qos.h to
> prevent linking error about multiple definition. Move DEFINE_PER_CPU
> for cpu_sqoscfg into qos.c
> - renamed qos prefix in function names to sqoscfg to be less generic
> - handle sqoscfg the same way has_vector and has_fpu are handled in the
> vector patch series
> - RFC v1: https://lore.kernel.org/linux-riscv/20230410043646.3138446-1-dfustini@baylibre.com/
>
> [1] https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
> [2] https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0
> [3] https://docs.kernel.org/filesystems/resctrl.html
> [4] https://lore.kernel.org/linux-riscv/20230419111111.477118-1-dfustini@baylibre.com/
> [5] https://github.com/tt-fustini/linux/tree/b4/cbqri-v6-17-rc5
> [6] https://github.com/tt-fustini/qemu/tree/riscv-cbqri-rqsc-pptt
> [7] https://github.com/tt-fustini/linux/tree/ssqosid-v6-17-rc5-debug
>
> Signed-off-by: Drew Fustini <fustini@kernel.org>
> ---
> Drew Fustini (2):
> RISC-V: Detect the Ssqosid extension
> RISC-V: Add support for srmcfg CSR from Ssqosid ext
>
> MAINTAINERS | 6 ++++++
> arch/riscv/Kconfig | 17 ++++++++++++++++
> arch/riscv/include/asm/csr.h | 8 ++++++++
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/include/asm/processor.h | 3 +++
> arch/riscv/include/asm/qos.h | 41 ++++++++++++++++++++++++++++++++++++++
> arch/riscv/include/asm/switch_to.h | 3 +++
> arch/riscv/kernel/cpufeature.c | 1 +
Why is there no binding change here? Is it not possible to use the
extension on DT systems, or is this an oversight?
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next prev parent reply other threads:[~2025-09-11 16:23 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-11 6:15 [PATCH 0/2] RISC-V: Detect Ssqosid extension and handle srmcfg CSR Drew Fustini
2025-09-11 6:15 ` [PATCH 1/2] RISC-V: Detect the Ssqosid extension Drew Fustini
2025-09-11 6:15 ` [PATCH 2/2] RISC-V: Add support for srmcfg CSR from Ssqosid ext Drew Fustini
2025-09-11 16:23 ` Conor Dooley [this message]
2025-09-11 19:53 ` [PATCH 0/2] RISC-V: Detect Ssqosid extension and handle srmcfg CSR Drew Fustini
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