From: Conor Dooley <conor@kernel.org>
To: Han Gao <rabenda.cn@gmail.com>
Cc: devicetree@vger.kernel.org, Drew Fustini <fustini@kernel.org>,
Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Han Gao <gaohan@iscas.ac.cn>
Subject: Re: [PATCH 2/3] riscv: dts: thead: add ziccrse for th1520
Date: Fri, 12 Sep 2025 18:57:19 +0100 [thread overview]
Message-ID: <20250912-gander-fox-d20c2e431816@spud> (raw)
In-Reply-To: <20250911184528.1512543-3-rabenda.cn@gmail.com>
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On Fri, Sep 12, 2025 at 02:45:27AM +0800, Han Gao wrote:
> th1520 support Ziccrse ISA extension [1].
>
> Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]
I don't see what this link has to do with th1520 supporting the
extension. The kernel supporting it has nothing to do with whether it
should be in the dts or not. A useful link would substantiate your
claim.
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
You only need to sign this off once.
Cheers,
Conor.
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++++++++++--------
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index 59d1927764a6..7f07688aa964 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -24,8 +24,10 @@ c910_0: cpu@0 {
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm", "xtheadvector";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "ziccrse", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> + "xtheadvector";
> thead,vlenb = <16>;
> reg = <0>;
> i-cache-block-size = <64>;
> @@ -49,8 +51,10 @@ c910_1: cpu@1 {
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm", "xtheadvector";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "ziccrse", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> + "xtheadvector";
> thead,vlenb = <16>;
> reg = <1>;
> i-cache-block-size = <64>;
> @@ -74,8 +78,10 @@ c910_2: cpu@2 {
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm", "xtheadvector";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "ziccrse", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> + "xtheadvector";
> thead,vlenb = <16>;
> reg = <2>;
> i-cache-block-size = <64>;
> @@ -99,8 +105,10 @@ c910_3: cpu@3 {
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm", "xtheadvector";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "ziccrse", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> + "xtheadvector";
> thead,vlenb = <16>;
> reg = <3>;
> i-cache-block-size = <64>;
> --
> 2.47.3
>
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next prev parent reply other threads:[~2025-09-12 17:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-11 18:45 [PATCH 0/3] riscv: dts: thead: add more th1520 isa extension support Han Gao
2025-09-11 18:45 ` [PATCH 1/3] riscv: dts: thead: add xtheadvector to the th1520 devicetree Han Gao
2025-09-11 18:45 ` [PATCH 2/3] riscv: dts: thead: add ziccrse for th1520 Han Gao
2025-09-12 17:57 ` Conor Dooley [this message]
2025-09-13 9:29 ` Han Gao
2025-09-11 18:45 ` [PATCH 3/3] riscv: dts: thead: add zfh " Han Gao
2025-09-12 17:59 ` Conor Dooley
2025-09-13 5:04 ` Guo Ren
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