From: "guoyaxing@bosc.ac.cn" <guoyaxing@bosc.ac.cn>
To: will <will@kernel.org>
Cc: linux-riscv <linux-riscv@lists.infradead.org>,
iommu <iommu@lists.linux.dev>, tjeznach <tjeznach@rivosinc.com>,
joro <joro@8bytes.org>, robin.murphy <robin.murphy@arm.com>,
paul.walmsley <paul.walmsley@sifive.com>,
palmer <palmer@dabbelt.com>, aou <aou@eecs.berkeley.edu>,
alex <alex@ghiti.fr>, anxu <anxu@bosc.ac.cn>,
wangran <wangran@bosc.ac.cn>
Subject: Re: Re: [PATCH v1 1/3] iommu/riscv: Add iommu perf driver
Date: Tue, 16 Sep 2025 18:27:23 +0800 [thread overview]
Message-ID: <202509161827232434929@bosc.ac.cn> (raw)
In-Reply-To: aMfsj1U7NY2m68T4@willie-the-truck
Hi, Will
From: Will Deacon
Date: 2025-09-15 18:38
To: Yaxing Guo
CC: linux-riscv; iommu; tjeznach; joro; robin.murphy; paul.walmsley; palmer; aou; alex; anxu; wangran
Subject: Re: [PATCH v1 1/3] iommu/riscv: Add iommu perf driver
On Mon, Sep 15, 2025 at 10:09:09AM +0800, Yaxing Guo wrote:
>> This patch introduces a performance monitor driver for RISC-V IOMMU
>> iohpm implementions that support hardware performance counters.
>> The driver expose RISC-V-IOMMU-specific performance events (eg. cycles,
>> tlb miss ...)through the Linux perf subsystem, enabling developers
>> to profile and optimize I/O translation performance.
>>
>> Key features:
>> - Implements a perf PMU driver for RISC-V IOMMU.
>>
>> - Exposes IOMMU perf events, such as 'cycles', 'tlb_miss'... via
>> /sys/devices/riscv-iommu-pmu/events/, allowing use with perf
>> tools:
>> perf stat -C 0 -e riscv-iommu-pmu/cycles/ ...
>> perf stat -C 0 -e riscv-iommu-pmu/tlb_miss/ ...
>> ...
>> - Supports event filtering through configureable attributes exposed
>> in /sys/devices/riscv-iommu-pmu/format/, including:
>> dv_gscv, pv_pscv，did_gscid，pid_pscid，idt (riscv iommu spec 5-23).
>>
>> - Implements overflow interrupt handling.
>>
>> - Adds device tree binding support via optional 'pmu-name' property
>> allowing platform-specific IOMMU implementations to specify a custom
>> defined event ID list. If not provided, the driver defaults to only
>> supporting 'cycles'. When set to 'dummy', it enables all 9 standard
>> event IDs as defined in riscv iommu spec(5-23).
>>
>> Signed-off-by: Yaxing Guo <guoyaxing@bosc.ac.cn>
>> ---
>> drivers/iommu/riscv/iommu-perf.c | 535 +++++++++++++++++++++++++++++++
>> drivers/iommu/riscv/iommu-perf.h | 88 +++++
>> drivers/iommu/riscv/iommu.h | 8 +
>> 3 files changed, 631 insertions(+)
>> create mode 100644 drivers/iommu/riscv/iommu-perf.c
>> create mode 100644 drivers/iommu/riscv/iommu-perf.h
> PMU drivers are better placed under drivers/perf/
> (the Arm SMMUv3 PMU driver lives there, for example).
I did a quick reading of SMMU pmu driver in drivers/perf/. However, If the RISC-V IOMMU PMU driver is placed under drivers/perf/ as the SMMU did, it would cause an overlap in the iomem resource region between the two devices(iommu & iommu pmu), because it needs to share interrupt-related registers (such as the IPSR register) with the main IOMMU driver.
Yaxing Guo
> Will
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next prev parent reply other threads:[~2025-09-16 10:27 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-15 2:09 [PATCH v1 1/3] iommu/riscv: Add iommu perf driver Yaxing Guo
2025-09-15 2:09 ` [PATCH v1 2/3] iommu/riscv: Add Makefile support for RISC-V IOMMU " Yaxing Guo
2025-09-16 3:40 ` kernel test robot
2025-09-15 2:09 ` [PATCH v1 3/3] iommu/riscv: Register RISC-V IOMMU PMU at init time Yaxing Guo
2025-09-15 10:38 ` [PATCH v1 1/3] iommu/riscv: Add iommu perf driver Will Deacon
2025-09-16 10:27 ` guoyaxing [this message]
2025-09-17 12:10 ` Will Deacon
2025-09-18 3:20 ` 郭亚星
2025-09-18 14:20 ` Will Deacon
2025-09-16 1:47 ` kernel test robot
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