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Tue, 23 Sep 2025 09:33:44 -0700 (PDT) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id 3f1490d57ef6-eb366bbfb29sm501295276.25.2025.09.23.09.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 09:33:44 -0700 (PDT) Date: Tue, 23 Sep 2025 11:33:43 -0500 From: Andrew Jones To: Jason Gunthorpe Cc: Thomas Gleixner , iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, zong.li@sifive.com, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atish.patra@linux.dev, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, alex@ghiti.fr Subject: Re: [RFC PATCH v2 08/18] iommu/riscv: Use MSI table to enable IMSIC access Message-ID: <20250923-b2caf55f4f87f05aaa619e0b@orel> References: <20250920203851.2205115-28-ajones@ventanamicro.com> <20250922184336.GD1391379@nvidia.com> <20250922-50372a07397db3155fec49c9@orel> <20250922235651.GG1391379@nvidia.com> <87ecrx4guz.ffs@tglx> <20250923140646.GM1391379@nvidia.com> <20250923-b85e3309c54eaff1cdfddcf9@orel> <20250923152702.GB2608121@nvidia.com> <20250923-e459316700c55d661c060b08@orel> <20250923162302.GC2608121@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250923162302.GC2608121@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250923_093346_308030_B22115BD X-CRM114-Status: GOOD ( 22.43 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Sep 23, 2025 at 01:23:02PM -0300, Jason Gunthorpe wrote: > On Tue, Sep 23, 2025 at 10:50:56AM -0500, Andrew Jones wrote: > > Yes, this is the part that I'd like to lean on you for, since I understand > > we want to avoid too much KVM/virt special casing for VFIO/IOMMUFD. I was > > thinking that if I bit the bullet and implemented nested support than when > > nesting was selected it would be apparent we're in virt context. However, > > I was hoping to pull together a solution that works with current QEMU and > > VFIO too. > > You probably do have to make nested part of this, but I don't have a > clear picture how you'd tie all the parts together through the nested > API.. > > Somehow you have to load a msiptp that is effectively linked to the > KVM reliably into the DC for the iommufd controlled devices that are > linked to that KVM. Then synchronize with VFIO that this is done and > it can setup KVM only interrupts somehow. This kvm entanglement is the > "virt" you have mentioned many times. Yes, the VFIO+KVM irqbypass framework currently provides much of this support (which patches 10-17 of this series leverage). But, if using nested is necessary in order to "signal" to the relevant subsystems that the device's irqs will truly be isolated, then I'll need to start figuring out how iommufd can fit into the mix (or if we'll need an iommufd-specific implementation for a new mix). > > The direct injection interrupt path is already quite a confusing > thing.. No argument there :-) Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv