From: Conor Dooley <conor@kernel.org>
To: soc@kernel.org
Cc: conor@kernel.org, linux-riscv@lists.infradead.org
Subject: [GIT PULL] RISC-V cache drivers for v6.18
Date: Wed, 24 Sep 2025 18:50:14 +0100 [thread overview]
Message-ID: <20250924-relenting-aqua-a4a93b89809e@spud> (raw)
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Hey Arnd,
Wee PR here with just two changes, for the standalone cache drivers that I
look after.
Cheers,
Conor.
The following changes since commit 8f5ae30d69d7543eee0d70083daf4de8fe15d585:
Linux 6.17-rc1 (2025-08-10 19:41:16 +0300)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-cache-for-v6.18
for you to fetch changes up to 941327ca5ddd45cfc4dd960cbbabed9e2b5cb1b0:
cache: sifive_ccache: Optimize cache flushes (2025-09-11 19:13:21 +0100)
----------------------------------------------------------------
RISC-V cache drivers for v6.18
sifive:
Reduce the number of fences issued while flushing. Samuel reports that
this is approximately a 15peed-up.
ax45mp:
Fix the binding so that it permits the cache-sets setting used by the
recently added QiLai SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
----------------------------------------------------------------
Conor Dooley (1):
dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value
Samuel Holland (1):
cache: sifive_ccache: Optimize cache flushes
.../devicetree/bindings/cache/andestech,ax45mp-cache.yaml | 6 +++++-
drivers/cache/sifive_ccache.c | 8 ++++----
2 files changed, 9 insertions(+), 5 deletions(-)
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