From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E96BCAC5B0 for ; Thu, 2 Oct 2025 11:05:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hJsjeCbsEE/JcNLMebh/io0Ek7s/wmVTVT8AyDktSfo=; b=nyYb0cSpYmqyIk ujK+MvdAmQkV0by4zBEhdtREb/nJFnKmy8OsiXlSrvcsdYl84DxmYVbxldzyzQxw2aBeMQdp67r+w atpFWucGti2MKMJtHQREZ3dmqM+TRaVWdFxsCDOGOWu5gBET5Qx/VaMy4K68vCdk5zv8XqIbXRkrO W0Dz/H/mjKvnNC45KW1gJ8OmCUH2XYbo/GXMQOkGnndro3j34msonOER4q0dpGqc40jXJfqfC2IU1 wNuJX86ODgbjwqohwDLGQRwKPlM7rhR4Wcdg1gJvPzG3mWH2bXrRCY0SrDLGkqo+qJQ3+vvfcFUd2 0ThOfdJNXevHKAwTGGdQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v4H7m-0000000AKj1-3FUb; Thu, 02 Oct 2025 11:05:26 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1v4H7k-0000000AKh9-2iby for linux-riscv@lists.infradead.org; Thu, 02 Oct 2025 11:05:26 +0000 Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 592Ao2lA070576 for ; Thu, 2 Oct 2025 18:50:02 +0800 (+08) (envelope-from randolph@andestech.com) Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 592AkDll068618 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 2 Oct 2025 18:46:13 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Thu, 2 Oct 2025 18:46:13 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v5 3/5] riscv: dts: andes: Add PCIe node into the QiLai SoC Date: Thu, 2 Oct 2025 18:45:56 +0800 Message-ID: <20251002104558.4068668-4-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251002104558.4068668-1-randolph@andestech.com> References: <20251002104558.4068668-1-randolph@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.173] X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 592Ao2lA070576 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251002_040525_005715_3EC154B8 X-CRM114-Status: UNSURE ( 8.45 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the Andes QiLai PCIe node, which includes 3 Root Complexes. Signed-off-by: Randolph Lin --- arch/riscv/boot/dts/andes/qilai.dtsi | 106 +++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi index de3de32f8c39..afa7b75a7e7a 100644 --- a/arch/riscv/boot/dts/andes/qilai.dtsi +++ b/arch/riscv/boot/dts/andes/qilai.dtsi @@ -182,5 +182,111 @@ uart0: serial@30300000 { reg-io-width = <4>; no-loopback-test; }; + + bus@80000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x20000000>, + <0x00 0x04000000 0x00 0x04000000 0x00 0x00001000>, + <0x00 0x00000000 0x20 0x00000000 0x20 0x00000000>; + + pcie@80000000 { + compatible = "andestech,qilai-pcie"; + device_type = "pci"; + reg = <0x00 0x80000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04000000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names = "dbi", "apb", "config"; + + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x1f 0x00000000>; + + #interrupt-cells = <1>; + interrupts = <0xf 0x4>; + interrupt-names = "msi"; + interrupt-parent = <&plic>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 1 &plic 0xf 0x4>, + <0 0 0 2 &plic 0xf 0x4>, + <0 0 0 3 &plic 0xf 0x4>, + <0 0 0 4 &plic 0xf 0x4>; + }; + }; + + bus@a0000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges = <0x00 0xa0000000 0x00 0xa0000000 0x00 0x20000000>, + <0x00 0x04001000 0x00 0x04001000 0x00 0x00001000>, + <0x00 0x00000000 0x10 0x00000000 0x08 0x00000000>; + + pcie@a0000000 { + compatible = "andestech,qilai-pcie"; + device_type = "pci"; + reg = <0x00 0xa0000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04001000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names = "dbi", "apb", "config"; + + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>; + + #interrupt-cells = <1>; + interrupts = <0xe 0x4>; + interrupt-names = "msi"; + interrupt-parent = <&plic>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 1 &plic 0xe 0x4>, + <0 0 0 2 &plic 0xe 0x4>, + <0 0 0 3 &plic 0xe 0x4>, + <0 0 0 4 &plic 0xe 0x4>; + }; + }; + + bus@c0000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges = <0x00 0xc0000000 0x00 0xc0000000 0x00 0x20000000>, + <0x00 0x04002000 0x00 0x04002000 0x00 0x00001000>, + <0x00 0x00000000 0x18 0x00000000 0x08 0x00000000>; + + pcie@c0000000 { + compatible = "andestech,qilai-pcie"; + device_type = "pci"; + reg = <0x00 0xc0000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04002000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names = "dbi", "apb", "config"; + + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>; + + #interrupt-cells = <1>; + interrupts = <0xd 0x4>; + interrupt-names = "msi"; + interrupt-parent = <&plic>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 1 &plic 0xd 0x4>, + <0 0 0 2 &plic 0xd 0x4>, + <0 0 0 3 &plic 0xd 0x4>, + <0 0 0 4 &plic 0xd 0x4>; + }; + }; + }; }; -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv