* [PATCH] dts: starfive: jh7110-common: split out mmc0 reset pins from common into boards
@ 2025-10-05 17:44 E Shattow
2025-10-20 17:36 ` Conor Dooley
0 siblings, 1 reply; 2+ messages in thread
From: E Shattow @ 2025-10-05 17:44 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti
Cc: E Shattow, linux-riscv, devicetree, linux-kernel
Prepare for Orange Pi RV using jh7110-common.dtsi having GPIO62 assignment
different than mmc0 reset by splitting this out into each board dts.
Signed-off-by: E Shattow <e@freeshell.de>
---
arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 11 -----------
.../dts/starfive/jh7110-deepcomputing-fml13v01.dts | 13 +++++++++++++
arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts | 13 +++++++++++++
.../boot/dts/starfive/jh7110-milkv-marscm.dtsi | 13 +++++++++++++
.../boot/dts/starfive/jh7110-pine64-star64.dts | 13 +++++++++++++
.../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 13 +++++++++++++
6 files changed, 65 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 5dc15e48b74b..083ec80b4e44 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -444,17 +444,6 @@ GPOEN_SYS_I2C6_DATA,
};
mmc0_pins: mmc0-0 {
- rst-pins {
- pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
- GPOEN_ENABLE,
- GPI_NONE)>;
- bias-pull-up;
- drive-strength = <12>;
- input-disable;
- input-schmitt-disable;
- slew-rate = <0>;
- };
-
mmc-pins {
pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
<PINMUX(PAD_SD0_CMD, 0)>,
diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
index f2857d021d68..0243e54a84ed 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
@@ -11,6 +11,19 @@ / {
compatible = "deepcomputing,fml13v01", "starfive,jh7110";
};
+&mmc0_pins {
+ rst-pins {
+ pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+};
+
&pcie1 {
perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
phys = <&pciephy1>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
index fdaf6b4557da..5ca10597dcd9 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
@@ -22,6 +22,19 @@ &i2c0 {
status = "okay";
};
+&mmc0_pins {
+ rst-pins {
+ pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+};
+
&pcie0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi
index 25b70af564ee..025471061d43 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi
@@ -40,6 +40,19 @@ &i2c6 {
status = "disabled";
};
+&mmc0_pins {
+ rst-pins {
+ pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+};
+
&mmc1 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
index 31e825be2065..980e24e3dbc8 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
@@ -44,6 +44,19 @@ &i2c0 {
status = "okay";
};
+&mmc0_pins {
+ rst-pins {
+ pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+};
+
&pcie1 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 5f14afb2c24d..574e128138c2 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -41,6 +41,19 @@ &mmc0 {
non-removable;
};
+&mmc0_pins {
+ rst-pins {
+ pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+};
+
&pcie0 {
status = "okay";
};
base-commit: 6093a688a07da07808f0122f9aa2a3eed250d853
--
2.50.0
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^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] dts: starfive: jh7110-common: split out mmc0 reset pins from common into boards
2025-10-05 17:44 [PATCH] dts: starfive: jh7110-common: split out mmc0 reset pins from common into boards E Shattow
@ 2025-10-20 17:36 ` Conor Dooley
0 siblings, 0 replies; 2+ messages in thread
From: Conor Dooley @ 2025-10-20 17:36 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, E Shattow
Cc: Conor Dooley, linux-riscv, devicetree, linux-kernel
From: Conor Dooley <conor.dooley@microchip.com>
On Sun, 05 Oct 2025 10:44:28 -0700, E Shattow wrote:
> Prepare for Orange Pi RV using jh7110-common.dtsi having GPIO62 assignment
> different than mmc0 reset by splitting this out into each board dts.
>
>
Applied to riscv-dt-for-next, thanks!
[1/1] dts: starfive: jh7110-common: split out mmc0 reset pins from common into boards
https://git.kernel.org/conor/c/fa939a287224
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 2+ messages in thread
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2025-10-20 17:36 ` Conor Dooley
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