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From: Drew Fustini <fustini@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Alexandre Ghiti <alex@ghiti.fr>, Conor Dooley <conor@kernel.org>,
	 Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>
Cc: "Kornel Dulęba" <mindal@semihalf.com>,
	"Adrien Ricciardi" <aricciardi@baylibre.com>,
	"James Morse" <james.morse@arm.com>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Atish Patra" <atish.patra@linux.dev>,
	"Vasudevan Srinivasan" <vasu@rivosinc.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, "Drew Fustini" <fustini@kernel.org>
Subject: [PATCH v4 2/3] RISC-V: Detect the Ssqosid extension
Date: Tue, 07 Oct 2025 23:21:11 -0700	[thread overview]
Message-ID: <20251007-ssqosid-v4-2-e8b57e59d812@kernel.org> (raw)
In-Reply-To: <20251007-ssqosid-v4-0-e8b57e59d812@kernel.org>

Ssqosid is the RISC-V Quality-of-Service (QoS) Identifiers specification
which defines the Supervisor Resource Management Configuration (srmcfg)
register.

Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
Signed-off-by: Kornel Dulęba <mindal@semihalf.com>
[fustini: rebase on riscv/for-next]
Signed-off-by: Drew Fustini <fustini@kernel.org>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index affd63e11b0a344c33a73647351ac02a94e42981..b4239f4f092d036ee3d037177b990e317d34a77f 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -106,6 +106,7 @@
 #define RISCV_ISA_EXT_ZAAMO		97
 #define RISCV_ISA_EXT_ZALRSC		98
 #define RISCV_ISA_EXT_ZICBOP		99
+#define RISCV_ISA_EXT_SSQOSID		100
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 67b59699357da8010db919b4ea2c24cd0d51182a..aeb14028bd91aa62bab854c87a11e20bdb848364 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -533,6 +533,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
 	__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
+	__RISCV_ISA_EXT_DATA(ssqosid, RISCV_ISA_EXT_SSQOSID),
 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
 	__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
 	__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),

-- 
2.34.1


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  parent reply	other threads:[~2025-10-08  6:21 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-08  6:21 [PATCH v4 0/3] RISC-V: Detect Ssqosid extension and handle srmcfg CSR Drew Fustini
2025-10-08  6:21 ` [PATCH v4 1/3] dt-bindings: riscv: Add Ssqosid extension description Drew Fustini
2025-10-08  6:21 ` Drew Fustini [this message]
2025-10-08  6:21 ` [PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext Drew Fustini
2025-10-09  6:47   ` Radim Krčmář
2025-10-11 18:35     ` Drew Fustini
2025-10-13  9:06       ` Radim Krčmář
2025-11-07 17:44         ` Drew Fustini
2025-10-10 12:23 ` [External] [PATCH v4 0/3] RISC-V: Detect Ssqosid extension and handle srmcfg CSR yunhui cui
2025-10-10 21:56   ` Drew Fustini

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