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Tue, 14 Oct 2025 00:33:55 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-426ce5e8a06sm22182799f8f.55.2025.10.14.00.33.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 00:33:55 -0700 (PDT) Date: Tue, 14 Oct 2025 10:33:51 +0300 From: Dan Carpenter To: oe-kbuild@lists.linux.dev, Randolph Lin , linux-kernel@vger.kernel.org Cc: lkp@intel.com, oe-kbuild-all@lists.linux.dev, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, alex@ghiti.fr, aou@eecs.berkeley.edu, palmer@dabbelt.com, paul.walmsley@sifive.com, ben717@andestech.com, inochiama@gmail.com, thippeswamy.havalige@amd.com, namcao@linutronix.de, shradha.t@samsung.com, pjw@kernel.org, randolph.sklin@gmail.com, tim609@andestech.com, Randolph Lin Subject: Re: [PATCH v6 4/5] PCI: andes: Add Andes QiLai SoC PCIe host driver support Message-ID: <202510092111.fZmvx6jO-lkp@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20251003023527.3284787-5-randolph@andestech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251014_003357_988460_3A3BBE23 X-CRM114-Status: UNSURE ( 8.26 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Randolph, kernel test robot noticed the following build warnings: https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Randolph-Lin/PCI-dwc-Allow-adjusting-the-number-of-ob-ib-windows-in-glue-driver/20251003-104100 base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next patch link: https://lore.kernel.org/r/20251003023527.3284787-5-randolph%40andestech.com patch subject: [PATCH v6 4/5] PCI: andes: Add Andes QiLai SoC PCIe host driver support config: powerpc-randconfig-r071-20251009 (https://download.01.org/0day-ci/archive/20251009/202510092111.fZmvx6jO-lkp@intel.com/config) compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 39f292ffa13d7ca0d1edff27ac8fd55024bb4d19) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Reported-by: Dan Carpenter | Closes: https://lore.kernel.org/r/202510092111.fZmvx6jO-lkp@intel.com/ smatch warnings: drivers/pci/controller/dwc/pcie-andes-qilai.c:157 qilai_pcie_host_fix_ob_iatu_count() error: uninitialized symbol 'ranges_32bits'. vim +/ranges_32bits +157 drivers/pci/controller/dwc/pcie-andes-qilai.c 816cad1ac60166 Randolph Lin 2025-10-03 133 static int qilai_pcie_host_fix_ob_iatu_count(struct dw_pcie_rp *pp) 816cad1ac60166 Randolph Lin 2025-10-03 134 { 816cad1ac60166 Randolph Lin 2025-10-03 135 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 816cad1ac60166 Randolph Lin 2025-10-03 136 struct device *dev = pci->dev; 816cad1ac60166 Randolph Lin 2025-10-03 137 struct resource_entry *entry; 816cad1ac60166 Randolph Lin 2025-10-03 138 /* Reserved 1 ob iATU for config space */ 816cad1ac60166 Randolph Lin 2025-10-03 139 int count = 1; 816cad1ac60166 Randolph Lin 2025-10-03 140 int ranges_32bits; This should be bool and initialized to false. 816cad1ac60166 Randolph Lin 2025-10-03 141 u64 pci_addr; 816cad1ac60166 Randolph Lin 2025-10-03 142 u64 size; 816cad1ac60166 Randolph Lin 2025-10-03 143 816cad1ac60166 Randolph Lin 2025-10-03 144 resource_list_for_each_entry(entry, &pp->bridge->windows) { 816cad1ac60166 Randolph Lin 2025-10-03 145 if (resource_type(entry->res) != IORESOURCE_MEM) 816cad1ac60166 Randolph Lin 2025-10-03 146 continue; 816cad1ac60166 Randolph Lin 2025-10-03 147 816cad1ac60166 Randolph Lin 2025-10-03 148 size = resource_size(entry->res); 816cad1ac60166 Randolph Lin 2025-10-03 149 if (size < SZ_4G) 816cad1ac60166 Randolph Lin 2025-10-03 150 count++; 816cad1ac60166 Randolph Lin 2025-10-03 151 816cad1ac60166 Randolph Lin 2025-10-03 152 pci_addr = entry->res->start - entry->offset; 816cad1ac60166 Randolph Lin 2025-10-03 153 if (pci_addr < SZ_4G) 816cad1ac60166 Randolph Lin 2025-10-03 154 ranges_32bits = true; 816cad1ac60166 Randolph Lin 2025-10-03 155 } 816cad1ac60166 Randolph Lin 2025-10-03 156 816cad1ac60166 Randolph Lin 2025-10-03 @157 if (!ranges_32bits) { 816cad1ac60166 Randolph Lin 2025-10-03 158 dev_err(dev, "Bridge window must contain 32-bits address\n"); 816cad1ac60166 Randolph Lin 2025-10-03 159 return -EINVAL; 816cad1ac60166 Randolph Lin 2025-10-03 160 } 816cad1ac60166 Randolph Lin 2025-10-03 161 816cad1ac60166 Randolph Lin 2025-10-03 162 pci->num_ob_windows = count; 816cad1ac60166 Randolph Lin 2025-10-03 163 816cad1ac60166 Randolph Lin 2025-10-03 164 return 0; 816cad1ac60166 Randolph Lin 2025-10-03 165 } -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv