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Wed, 15 Oct 2025 07:31:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG683Uu0GDZc9bo630j+NWQaTw6T0Q6n9Za7jgl4kwN5Wnz8kfYe9OZzC9Ddj1aZld04KGuRA== X-Received: by 2002:a05:600d:11:b0:46f:b43a:aedf with SMTP id 5b1f17b1804b1-46fb43aaf25mr108180605e9.38.1760538677489; Wed, 15 Oct 2025 07:31:17 -0700 (PDT) Received: from holism.lzampier.com ([2a06:5900:814a:ab00:c1c7:2e09:633d:e94e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47101c02377sm32617005e9.6.2025.10.15.07.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Oct 2025 07:31:17 -0700 (PDT) From: Lucas Zampieri To: linux-kernel@vger.kernel.org Cc: Charles Mirabile , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Vivian Wang , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley , Lucas Zampieri Subject: [PATCH v4 2/3] dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC Date: Wed, 15 Oct 2025 15:31:06 +0100 Message-ID: <20251015143108.441291-3-lzampier@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251015143108.441291-1-lzampier@redhat.com> References: <20251015143108.441291-1-lzampier@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: ygC_yOB09wvdqc5blGv0h0oNKXD9tpjzYGBBsu1L77M_1760538678 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251015_073122_539945_849727CF X-CRM114-Status: UNSURE ( 9.22 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Charles Mirabile Add compatible strings for the PLIC found in UltraRISC DP1000 SoC. The PLIC is part of the UR-CP100 core and has a hardware bug requiring a workaround. Signed-off-by: Charles Mirabile Acked-by: Conor Dooley Signed-off-by: Lucas Zampieri --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 5b827bc24301..34591d64cca3 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -74,6 +74,9 @@ properties: - sophgo,sg2044-plic - thead,th1520-plic - const: thead,c900-plic + - items: + - const: ultrarisc,dp1000-plic + - const: ultrarisc,cp100-plic - items: - const: sifive,plic-1.0.0 - const: riscv,plic0 -- 2.51.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv