From: Joshua Milas <josh.milas@gmail.com>
To: tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, unicorn_wang@outlook.com,
inochiama@gmail.com, paul.walmsley@sifive.com,
samuel.holland@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr,
alexander.sverdlin@gmail.com, rabenda.cn@gmail.com,
thomas.bonnefille@bootlin.com, chao.wei@sophgo.com,
liujingqi@lanxincomputing.com
Cc: josh.milas@gmail.com, devicetree@vger.kernel.org,
sophgo@lists.linux.dev, linux-riscv@lists.infradead.org
Subject: [PATCH v3 4/5] riscv64: dts: sophgo: add SG2000 dtsi
Date: Tue, 28 Oct 2025 20:10:51 -0400 [thread overview]
Message-ID: <20251029001052.36774-5-josh.milas@gmail.com> (raw)
In-Reply-To: <20251029001052.36774-1-josh.milas@gmail.com>
Adds sg2000.dtsi on the RISCV side.
Signed-off-by: Joshua Milas <josh.milas@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2000.dtsi | 53 ++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/sg2000.dtsi
diff --git a/arch/riscv/boot/dts/sophgo/sg2000.dtsi b/arch/riscv/boot/dts/sophgo/sg2000.dtsi
new file mode 100644
index 0000000000000..412adacc00576
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2000.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/pinctrl-sg2000.h>
+#include "cv180x-cpus.dtsi"
+#include "cv180x.dtsi"
+#include "cv181x.dtsi"
+
+/ {
+ compatible = "sophgo,sg2000";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+
+ soc {
+ interrupt-parent = <&plic>;
+ dma-noncoherent;
+
+ pinctrl: pinctrl@3001000 {
+ compatible = "sophgo,sg2000-pinctrl";
+ reg = <0x03001000 0x1000>,
+ <0x05027000 0x1000>;
+ reg-names = "sys", "rtc";
+ };
+
+ clk: clock-controller@3002000 {
+ compatible = "sophgo,sg2000-clk";
+ reg = <0x03002000 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+ plic: interrupt-controller@70000000 {
+ compatible = "sophgo,sg2000-plic", "thead,c900-plic";
+ reg = <0x70000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <101>;
+ };
+
+ clint: timer@74000000 {
+ compatible = "sophgo,sg2000-clint", "thead,c900-clint";
+ reg = <0x74000000 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
+ };
+};
--
2.51.1
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next prev parent reply other threads:[~2025-10-29 0:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-29 0:10 [PATCH v3 0/5] Add initial Milk-V Duo S board support Joshua Milas
2025-10-29 0:10 ` [PATCH v3 1/5] dt-bindings: soc: sophgo: add Milk-V Duo S board compatibles Joshua Milas
2025-10-29 5:58 ` Krzysztof Kozlowski
2025-10-29 0:10 ` [PATCH v3 2/5] arm64: dts: sophgo: add initial Milk-V Duo S board support Joshua Milas
2025-10-29 12:35 ` Michael Opdenacker
2025-10-29 14:41 ` Michael Opdenacker
2025-10-29 0:10 ` [PATCH v3 3/5] dt-bindings: soc: sophgo: add sg2000 plic and clint documentation Joshua Milas
2025-10-29 0:10 ` Joshua Milas [this message]
2025-10-29 0:10 ` [PATCH v3 5/5] riscv64: dts: sophgo: add initial Milk-V Duo S board support Joshua Milas
2025-10-29 5:57 ` [PATCH v3 0/5] Add " Krzysztof Kozlowski
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