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Wed, 29 Oct 2025 04:27:34 -0700 (PDT) Received: from ventana-desktop.localhost ([2405:201:d019:c0ce:f7f5:7789:48e5:c03f]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33fed7f6040sm15316918a91.16.2025.10.29.04.27.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 04:27:33 -0700 (PDT) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, acpica-devel@lists.linux.dev Subject: [RFC PATCH v2 06/10] riscv: Add functions to register ghes having SSE notification Date: Wed, 29 Oct 2025 16:56:44 +0530 Message-ID: <20251029112649.3811657-7-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029112649.3811657-1-hchauhan@ventanamicro.com> References: <20251029112649.3811657-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251029_042735_318048_C5EF7CD6 X-CRM114-Status: GOOD ( 14.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: apatel@ventanamicro.com, cleger@rivosinc.com, tony.luck@intel.com, Himanshu Chauhan , robert.moore@intel.com, conor@kernel.org, james.morse@arm.com, paul.walmsley@sifive.com, palmer@dabbelt.com, ardb@kernel.org, lenb@kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add functions to register the ghes entries which have SSE as notification type. The vector inside the ghes is the SSE event ID that should be registered. Signed-off-by: Himanshu Chauhan --- drivers/firmware/riscv/riscv_sbi_sse.c | 147 +++++++++++++++++++++++++ include/linux/riscv_sbi_sse.h | 16 +++ 2 files changed, 163 insertions(+) diff --git a/drivers/firmware/riscv/riscv_sbi_sse.c b/drivers/firmware/riscv/riscv_sbi_sse.c index 6561c7acdaaa..46ebc9e9651c 100644 --- a/drivers/firmware/riscv/riscv_sbi_sse.c +++ b/drivers/firmware/riscv/riscv_sbi_sse.c @@ -5,6 +5,8 @@ #define pr_fmt(fmt) "sse: " fmt +#include +#include #include #include #include @@ -700,3 +702,148 @@ static int __init sse_init(void) return ret; } arch_initcall(sse_init); + +struct sse_ghes_callback { + struct list_head head; + struct ghes *ghes; + sse_event_handler_fn *callback; +}; + +struct sse_ghes_event_data { + struct list_head head; + u32 event_num; + struct list_head callback_list; + struct sse_event *event; +}; + +static DEFINE_SPINLOCK(sse_ghes_event_list_lock); +static LIST_HEAD(sse_ghes_event_list); + +static int sse_ghes_handler(u32 event_num, void *arg, struct pt_regs *regs) +{ + struct sse_ghes_event_data *ev_data = arg; + struct sse_ghes_callback *cb = NULL; + + list_for_each_entry(cb, &ev_data->callback_list, head) { + if (cb && cb->ghes && cb->callback) { + cb->callback(ev_data->event_num, cb->ghes, regs); + } + } + + return 0; +} + +int sse_register_ghes(struct ghes *ghes, sse_event_handler_fn *lo_cb, + sse_event_handler_fn *hi_cb) +{ + struct sse_ghes_event_data *ev_data, *evd; + struct sse_ghes_callback *cb; + u32 ev_num; + int err; + + if (!sse_available) + return -EOPNOTSUPP; + if (!ghes || !lo_cb || !hi_cb) + return -EINVAL; + + ev_num = ghes->generic->notify.vector; + + ev_data = NULL; + spin_lock(&sse_ghes_event_list_lock); + list_for_each_entry(evd, &sse_ghes_event_list, head) { + if (evd->event_num == ev_num) { + ev_data = evd; + break; + } + } + spin_unlock(&sse_ghes_event_list_lock); + + if (!ev_data) { + ev_data = kzalloc(sizeof(*ev_data), GFP_KERNEL); + if (!ev_data) + return -ENOMEM; + + INIT_LIST_HEAD(&ev_data->head); + ev_data->event_num = ev_num; + + INIT_LIST_HEAD(&ev_data->callback_list); + + ev_data->event = sse_event_register(ev_num, ev_num, + sse_ghes_handler, ev_data); + if (IS_ERR(ev_data->event)) { + pr_err("%s: Couldn't register event 0x%x\n", __func__, ev_num); + kfree(ev_data); + return -ENOMEM; + } + + err = sse_event_enable(ev_data->event); + if (err) { + pr_err("%s: Couldn't enable event 0x%x\n", __func__, ev_num); + sse_event_unregister(ev_data->event); + kfree(ev_data); + return err; + } + + spin_lock(&sse_ghes_event_list_lock); + list_add_tail(&ev_data->head, &sse_ghes_event_list); + spin_unlock(&sse_ghes_event_list_lock); + } + + list_for_each_entry(cb, &ev_data->callback_list, head) { + if (cb->ghes == ghes) + return -EALREADY; + } + + cb = kzalloc(sizeof(*cb), GFP_KERNEL); + if (!cb) + return -ENOMEM; + INIT_LIST_HEAD(&cb->head); + cb->ghes = ghes; + cb->callback = lo_cb; + list_add_tail(&cb->head, &ev_data->callback_list); + + return 0; +} + +int sse_unregister_ghes(struct ghes *ghes) +{ + struct sse_ghes_event_data *ev_data, *tmp; + struct sse_ghes_callback *cb; + int free_ev_data = 0; + + if (!ghes) + return -EINVAL; + + spin_lock(&sse_ghes_event_list_lock); + + list_for_each_entry_safe(ev_data, tmp, &sse_ghes_event_list, head) { + list_for_each_entry(cb, &ev_data->callback_list, head) { + if (cb->ghes != ghes) + continue; + + list_del(&cb->head); + kfree(cb); + break; + } + + if (list_empty(&ev_data->callback_list)) + free_ev_data = 1; + + if (free_ev_data) { + spin_unlock(&sse_ghes_event_list_lock); + + sse_event_disable(ev_data->event); + sse_event_unregister(ev_data->event); + ev_data->event = NULL; + + spin_lock(&sse_ghes_event_list_lock); + + list_del(&ev_data->head); + kfree(ev_data); + } + } + + spin_unlock(&sse_ghes_event_list_lock); + + return 0; +} diff --git a/include/linux/riscv_sbi_sse.h b/include/linux/riscv_sbi_sse.h index a1b58e89dd19..cd615b479f82 100644 --- a/include/linux/riscv_sbi_sse.h +++ b/include/linux/riscv_sbi_sse.h @@ -11,6 +11,7 @@ struct sse_event; struct pt_regs; +struct ghes; typedef int (sse_event_handler_fn)(u32 event_num, void *arg, struct pt_regs *regs); @@ -24,6 +25,10 @@ void sse_event_unregister(struct sse_event *evt); int sse_event_set_target_cpu(struct sse_event *sse_evt, unsigned int cpu); +int sse_register_ghes(struct ghes *ghes, sse_event_handler_fn *lo_cb, + sse_event_handler_fn *hi_cb); +int sse_unregister_ghes(struct ghes *ghes); + int sse_event_enable(struct sse_event *sse_evt); void sse_event_disable(struct sse_event *sse_evt); @@ -47,6 +52,17 @@ static inline int sse_event_set_target_cpu(struct sse_event *sse_evt, return -EOPNOTSUPP; } +static inline int sse_register_ghes(struct ghes *ghes, sse_event_handler_fn *lo_cb, + sse_event_handler_fn *hi_cb) +{ + return -EOPNOTSUPP; +} + +static inline int sse_unregister_ghes(struct ghes *ghes) +{ + return -EOPNOTSUPP; +} + static inline int sse_event_enable(struct sse_event *sse_evt) { return -EOPNOTSUPP; -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv