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Wed, 29 Oct 2025 04:27:39 -0700 (PDT) Received: from ventana-desktop.localhost ([2405:201:d019:c0ce:f7f5:7789:48e5:c03f]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33fed7f6040sm15316918a91.16.2025.10.29.04.27.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 04:27:38 -0700 (PDT) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, acpica-devel@lists.linux.dev Subject: [RFC PATCH v2 07/10] riscv: Add RISC-V entries in processor type and ISA strings Date: Wed, 29 Oct 2025 16:56:45 +0530 Message-ID: <20251029112649.3811657-8-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029112649.3811657-1-hchauhan@ventanamicro.com> References: <20251029112649.3811657-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251029_042740_279061_EA8AA4BF X-CRM114-Status: UNSURE ( 8.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: apatel@ventanamicro.com, cleger@rivosinc.com, tony.luck@intel.com, Himanshu Chauhan , robert.moore@intel.com, conor@kernel.org, james.morse@arm.com, paul.walmsley@sifive.com, palmer@dabbelt.com, ardb@kernel.org, lenb@kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add RISCV and RISCV32/64 strings in the in processor type and ISA strings respectively. These are defined for cper records. Signed-off-by: Himanshu Chauhan --- drivers/firmware/efi/cper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c index 928409199a1a..ebdd92ba1e15 100644 --- a/drivers/firmware/efi/cper.c +++ b/drivers/firmware/efi/cper.c @@ -110,6 +110,7 @@ static const char * const proc_type_strs[] = { "IA32/X64", "IA64", "ARM", + "RISCV", }; static const char * const proc_isa_strs[] = { @@ -118,6 +119,8 @@ static const char * const proc_isa_strs[] = { "X64", "ARM A32/T32", "ARM A64", + "RISCV32", + "RISCV64", }; const char * const cper_proc_error_type_strs[] = { -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv