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Thu, 30 Oct 2025 06:57:02 -0700 (PDT) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.55]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498e495e8sm187071905ad.110.2025.10.30.06.56.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Oct 2025 06:57:02 -0700 (PDT) From: Xu Lu To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, apatel@ventanamicro.com, guoren@kernel.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [RFC PATCH v1 0/4] riscv: mm: Defer tlb flush to context_switch Date: Thu, 30 Oct 2025 21:56:48 +0800 Message-ID: <20251030135652.63837-1-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.50.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251030_065706_085918_51AD02B7 X-CRM114-Status: UNSURE ( 9.10 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When need to flush tlb of a remote cpu, there is no need to send an IPI if the target cpu is not using the asid we want to flush. Instead, we can cache the tlb flush info in percpu buffer, and defer the tlb flush to the next context_switch. This reduces the number of IPI due to tlb flush: * ltp - mmapstress01 Before: ~108k After: ~46k Future plan in the next version: - This patch series reduces IPI by deferring tlb flush to context_switch. It does not clear the mm_cpumask of target mm_struct. In the next version, I will apply a threshold to the number of ASIDs maintained by each cpu's tlb. Once the threshold is exceeded, ASID that has not been used for the longest time will be flushed out. And current cpu will be cleared in the mm_cpumask. Thanks in advance for your comments. Xu Lu (4): riscv: mm: Introduce percpu loaded_asid riscv: mm: Introduce percpu tlb flush queue riscv: mm: Enqueue tlbflush info if task is not running on target cpu riscv: mm: Perform tlb flush during context_switch arch/riscv/include/asm/mmu_context.h | 1 + arch/riscv/include/asm/tlbflush.h | 4 ++ arch/riscv/mm/context.c | 10 ++++ arch/riscv/mm/tlbflush.c | 76 +++++++++++++++++++++++++++- 4 files changed, 90 insertions(+), 1 deletion(-) -- 2.20.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv