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Thu, 30 Oct 2025 06:57:06 -0700 (PDT) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.55]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498e495e8sm187071905ad.110.2025.10.30.06.57.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 30 Oct 2025 06:57:06 -0700 (PDT) From: Xu Lu To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, apatel@ventanamicro.com, guoren@kernel.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [RFC PATCH v1 1/4] riscv: mm: Introduce percpu loaded_asid Date: Thu, 30 Oct 2025 21:56:49 +0800 Message-ID: <20251030135652.63837-2-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251030135652.63837-1-luxu.kernel@bytedance.com> References: <20251030135652.63837-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251030_065707_896067_0B46090D X-CRM114-Status: UNSURE ( 8.96 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The percpu loaded_asid records the asid currently used by each CPU. Signed-off-by: Xu Lu --- arch/riscv/include/asm/mmu_context.h | 1 + arch/riscv/mm/context.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h index 8c4bc49a3a0f5..fd532f8e8d057 100644 --- a/arch/riscv/include/asm/mmu_context.h +++ b/arch/riscv/include/asm/mmu_context.h @@ -39,6 +39,7 @@ static inline int init_new_context(struct task_struct *tsk, } DECLARE_STATIC_KEY_FALSE(use_asid_allocator); +DECLARE_PER_CPU(unsigned long, loaded_asid); #ifdef CONFIG_RISCV_ISA_SUPM #define mm_untag_mask mm_untag_mask diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 55c20ad1f7444..4d5792c3a8c19 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -32,6 +32,8 @@ static unsigned long *context_asid_map; static DEFINE_PER_CPU(atomic_long_t, active_context); static DEFINE_PER_CPU(unsigned long, reserved_context); +DEFINE_PER_CPU(unsigned long, loaded_asid) = 0; + static bool check_update_reserved_context(unsigned long cntx, unsigned long newcntx) { @@ -193,6 +195,8 @@ static void set_mm_asid(struct mm_struct *mm, unsigned int cpu) (cntx2asid(cntx) << SATP_ASID_SHIFT) | satp_mode); + this_cpu_write(loaded_asid, cntx2asid(cntx)); + if (need_flush_tlb) local_flush_tlb_all(); } -- 2.20.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv