[PATCH v3 0/3] Add support for Microchip CoreSPI Controller

[Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>]

This patch series adds support for the Microchip FPGA CoreSPI "soft" IP 
and documents its device tree bindings.

As preparation, the existing Microchip SPI driver is renamed to clearly
indicate that it supports only the Microchip PolarFire SoC "hard" controller.
Although it was originally named with the expectation that it might also
cover the FPGA CoreSPI "soft" IP, the register layouts differ significantly, 
so separate drivers are required.

changes in v3
--------------
- Renamed Kconfig symbol to SPI_MICROCHIP_CORE_SPI 
- Renamed CoreSPI driver from spi-microchip-core.c to spi-microchip-core-spi.c to avoid confusion

changes in v2
--------------
- Moved compatible strings into an enum and kept alphabetical order
- Replaced .remove_new callback with .remove
- Dropped unused variable reported by kernel test robot 
- Updated CoreSPI drivers commit message to include the 8-bit frame size restriction

Prajna Rajendra Kumar (3):
  spi: microchip: rename driver file and internal identifiers
  spi: dt-binding: document Microchip CoreSPI
  spi: add support for microchip "soft" spi controller

 .../bindings/spi/microchip,mpfs-spi.yaml      |  70 ++-
 drivers/spi/Kconfig                           |  28 +-
 drivers/spi/Makefile                          |   3 +-
 drivers/spi/spi-microchip-core-spi.c          | 442 ++++++++++++++++++
 .../spi/{spi-microchip-core.c => spi-mpfs.c}  | 207 ++++----
 5 files changed, 635 insertions(+), 115 deletions(-)
 create mode 100644 drivers/spi/spi-microchip-core-spi.c
 rename drivers/spi/{spi-microchip-core.c => spi-mpfs.c} (68%)

-- 
2.25.1


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