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[123.225.39.221]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11f283d4733sm10364600c88.17.2025.12.10.08.13.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 08:13:48 -0800 (PST) From: Charlie Jenkins X-Google-Original-From: Charlie Jenkins Subject: [PATCH RFC 00/10] riscv: Add support for rva23 Date: Wed, 10 Dec 2025 08:13:37 -0800 Message-Id: <20251210-profiles-v1-0-315a6ff2ca5a@gmail.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIADKcOWkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1MDM0Mz3YKi/LTMnNRiXcvkZDPjVCPLRMsUSyWg8oKi1LTMCrBR0UpBbs5 KsbW1AAQ7ZHNfAAAA X-Change-ID: 20250616-profiles-9cc63e29a9d9 To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Samuel Holland , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Luke Nelson , Xi Wang , Eric Biggers , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765383226; l=5445; i=thecharlesjenkins@gmail.com; s=20240124; h=from:subject:message-id; bh=oDpw19AYDhsKPqwE33ZOXFntcgHiTkEc0I/reT1h7bY=; b=9G4zeg8W+7TphoTpqoxfI/PgUdvZNYbekQnflf1mLkM4AKNenR5ilmOFJ6ItRvna9a0yuzgdZ EYeDyKYuM8vAv8LEIyhjdto0y2zVQXfMH3AA3dyJCmGedWKZu+X8M+p X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=eVndo3OHViAjwuqHqbJB4ZtzJzzvk/r6fUf84tZ3rw4= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251210_081350_374068_C6CE9399 X-CRM114-Status: UNSURE ( 9.70 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org I will be talking about rva23 at Plumbers this year and have this series as a draft of my ideas. rva23 is a RVI profile to group together extensions that are expected to be found on high-performance systems. This series: 1. Introduces a framework to add extensions to the kernel cflags 2. Adds a rva23 config option 3. Optimizes riscv_has_extension_* This is based on 6.18 plus https://lore.kernel.org/linux-riscv/20251020-riscv-altn-helper-wip-v4-0-ef941c87669a@iscas.ac.cn/. Signed-off-by: Charlie Jenkins --- Charlie Jenkins (10): riscv: Standardize extension capitilization riscv: kconfig: Reorganize extensions riscv: kconfig: Simply arch selection riscv: kconfig: Make extensions tristate riscv: kconfig: Add zve32x riscv: Makefile: Add enabled extensions to compiler flags riscv: kconfig: Make vendor extensions tristate riscv: Optimize cpufeature macros for extension assumptions riscv: kconfig: Add rva23 config riscv: csum: Remove inline assembly arch/riscv/Kconfig | 340 +-------------- arch/riscv/Kconfig.extensions | 485 +++++++++++++++++++++ arch/riscv/Kconfig.vendor | 25 +- arch/riscv/Makefile | 136 +++++- arch/riscv/include/asm/arch_hweight.h | 4 +- arch/riscv/include/asm/archrandom.h | 2 +- arch/riscv/include/asm/asm-prototypes.h | 2 +- arch/riscv/include/asm/barrier.h | 2 +- arch/riscv/include/asm/bitops.h | 8 +- arch/riscv/include/asm/checksum.h | 32 -- arch/riscv/include/asm/cmpxchg.h | 14 +- arch/riscv/include/asm/cpufeature-macros.h | 136 ++++-- arch/riscv/include/asm/cpufeature.h | 42 +- arch/riscv/include/asm/hugetlb.h | 2 +- arch/riscv/include/asm/hwcap.h | 18 +- arch/riscv/include/asm/kgdb.h | 2 +- arch/riscv/include/asm/kvm_vcpu_vector.h | 2 +- arch/riscv/include/asm/mmu.h | 2 +- arch/riscv/include/asm/mmu_context.h | 4 +- arch/riscv/include/asm/page.h | 2 +- arch/riscv/include/asm/pgtable-64.h | 2 +- arch/riscv/include/asm/pgtable.h | 6 +- arch/riscv/include/asm/processor.h | 2 +- arch/riscv/include/asm/simd.h | 2 +- arch/riscv/include/asm/swab.h | 2 +- arch/riscv/include/asm/switch_to.h | 4 +- arch/riscv/include/asm/uaccess.h | 2 +- arch/riscv/include/asm/uprobes.h | 2 +- arch/riscv/include/asm/vector.h | 7 +- arch/riscv/include/asm/vendor_extensions.h | 113 ++--- arch/riscv/include/asm/xor.h | 2 +- arch/riscv/kernel/Makefile | 6 +- arch/riscv/kernel/cpufeature.c | 38 +- arch/riscv/kernel/head.S | 2 +- arch/riscv/kernel/kgdb.c | 2 +- arch/riscv/kernel/pi/archrandom_early.c | 1 + arch/riscv/kernel/probes/decode-insn.c | 2 +- arch/riscv/kernel/probes/uprobes.c | 2 +- arch/riscv/kernel/process.c | 10 +- arch/riscv/kernel/ptrace.c | 12 +- arch/riscv/kernel/signal.c | 2 +- arch/riscv/kernel/suspend.c | 8 +- arch/riscv/kernel/sys_hwprobe.c | 4 +- arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S | 6 +- arch/riscv/kernel/vendor_extensions/Makefile | 22 +- arch/riscv/kvm/tlb.c | 2 +- arch/riscv/kvm/vcpu.c | 10 +- arch/riscv/kvm/vcpu_onereg.c | 22 +- arch/riscv/kvm/vcpu_vector.c | 2 +- arch/riscv/lib/Makefile | 14 +- arch/riscv/lib/csum.c | 94 ---- arch/riscv/lib/strcmp.S | 2 +- arch/riscv/lib/strlen.S | 2 +- arch/riscv/lib/strncmp.S | 2 +- arch/riscv/lib/uaccess.S | 4 +- arch/riscv/mm/hugetlbpage.c | 2 +- arch/riscv/mm/pgtable.c | 2 +- arch/riscv/mm/tlbflush.c | 2 +- arch/riscv/net/bpf_jit.h | 2 +- drivers/perf/Kconfig | 2 +- drivers/perf/riscv_pmu_sbi.c | 3 +- lib/crc/riscv/crc-t10dif.h | 2 +- lib/crc/riscv/crc32.h | 8 +- lib/crc/riscv/crc64.h | 4 +- lib/raid6/Makefile | 4 +- lib/raid6/algos.c | 4 +- 66 files changed, 961 insertions(+), 749 deletions(-) --- base-commit: 537904d2226574c759e51bdf301ca8a90d0fdce1 change-id: 20250616-profiles-9cc63e29a9d9 Best regards, -- Charlie Jenkins _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv