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Mon, 22 Dec 2025 05:06:12 -0800 (PST) Received: from [127.0.1.1] ([2a12:a305:4::402f]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34e70c932casm12970405a91.0.2025.12.22.05.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 05:06:11 -0800 (PST) From: Guodong Xu Subject: [PATCH v2 00/13] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board Date: Mon, 22 Dec 2025 21:04:10 +0800 Message-Id: <20251222-k3-basic-dt-v2-0-3af3f3cd0f8a@riscstar.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAMpBSWkC/23MQQrCMBCF4auUWTuSRFOMK+8hXcRJtIPYlplQl NK7G7t2+T943wKahbPCuVlA8szK41DD7RqgPg6PjJxqgzPOW2dbfB7wFpUJU0FKwR+NaW04Bai PSfKd35t27Wr3rGWUz4bP9rf+d2aLBqNJzrcUEgV3EVbSEmVP4wu6dV2/t9tfw6kAAAA= X-Change-ID: 20251216-k3-basic-dt-cd9540061989 To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu , Heinrich Schuchardt , Conor Dooley X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251222_050614_110506_A8A71C93 X-CRM114-Status: GOOD ( 11.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series introduces basic support for the SpacemiT K3 SoC and the K3 Pico-ITX evaluation board. This series (starting from v2) also adds descriptions about ISA extensions mandated by the RVA23 Profile Version 1.0 into riscv/extensions.yaml. These additions are implemented in Patches 7 through 11. The SpacemiT K3 is an SoC featuring 8 SpacemiT X100 RISC-V cores. The X100 is a 4-issue, out-of-order core compliant with the RVA23 profile, targeting high-performance scenarios. [1] The K3 Pico-ITX is an evaluation board built around the K3 SoC. >From an RVA23 profile compliance perspective, the X100 supports all mandatory extensions required by RVA23U64 and RVA23S64. This v2 series includes: - DT bindings for SpacemiT X100 core, K3 SoC, and Pico-ITX board. - DT bindings for K3 integrated peripherals: CLINT, APLIC, IMSIC, and UART. - Initial Device Tree for K3 SoC and Pico-ITX board. - Add DT bindings for mandatory extensions of RVA23. This series has been rebased to v6.19-rc2. Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] Patches 7 and 8 from the v1 series have been renumbered to Patches 12 and 13. Changes in v2: - Patch 1: Fixed alphanumeric sorting order of compatible strings (swapped x100 and x60) as per Krzysztof's feedback. Update commit message with more information about X100 featurs per Yixun's feedback. - Patch 4: Fixed the order to keep things alphabetically. - Patch 6: Use "one blank space" between name and email address. - Patch 7 ~ 11: New patches. Add description of RVA23 mandatory extensions into riscv binding YAML file. - Patch 12 (Patch 7 in v1): Removed aliases node. Updated 'riscv,isa-extensions' with new extension strings available - Patch 13 (Patch 8 in v1): Updated the memory address to the hardware truth. Added aliases node in board dts. - Patch 1,2,3,5: Add Reviewed-by and Acked-by collected. Link to v1: https://lore.kernel.org/r/20251216-k3-basic-dt-v1-0-a0d256c9dc92@riscstar.com Signed-off-by: Guodong Xu --- Guodong Xu (13): dt-bindings: riscv: add SpacemiT X100 CPU compatible dt-bindings: timer: add SpacemiT K3 CLINT dt-bindings: interrupt-controller: add SpacemiT K3 APLIC dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC dt-bindings: serial: 8250: add SpacemiT K3 UART compatible dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings dt-bindings: riscv: Add B ISA extension description dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl dt-bindings: riscv: Add Sha and its comprised extensions dt-bindings: riscv: Add Supm extension description riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC riscv: dts: spacemit: add SpacemiT K3 Pico-ITX board device tree .../bindings/interrupt-controller/riscv,aplic.yaml | 1 + .../interrupt-controller/riscv,imsics.yaml | 1 + Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/riscv/extensions.yaml | 180 +++++++ .../devicetree/bindings/riscv/spacemit.yaml | 4 + Documentation/devicetree/bindings/serial/8250.yaml | 1 + .../devicetree/bindings/timer/sifive,clint.yaml | 1 + arch/riscv/boot/dts/spacemit/Makefile | 1 + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 38 ++ arch/riscv/boot/dts/spacemit/k3.dtsi | 548 +++++++++++++++++++++ 10 files changed, 776 insertions(+) --- base-commit: 9448598b22c50c8a5bb77a9103e2d49f134c9578 change-id: 20251216-k3-basic-dt-cd9540061989 Best regards, -- Guodong Xu _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv