From: Guodong Xu <guodong@riscstar.com>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Yixun Lan <dlan@gentoo.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>,
Anup Patel <anup@brainfault.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Lubomir Rintel <lkundrak@v3.sk>, Yangyu Chen <cyy@cyyself.name>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
Kevin Meng Zhang <zhangmeng.kevin@linux.spacemit.com>,
Anup Patel <anup@brainfault.org>,
Andrew Jones <ajones@ventanamicro.com>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, spacemit@lists.linux.dev,
linux-serial@vger.kernel.org, Guodong Xu <guodong@riscstar.com>
Subject: [PATCH v4 09/11] dt-bindings: riscv: Add Sha and its comprised extensions
Date: Sat, 10 Jan 2026 13:18:21 +0800 [thread overview]
Message-ID: <20260110-k3-basic-dt-v4-9-d492f3a30ffa@riscstar.com> (raw)
In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com>
Add descriptions for the Sha extension and the seven extensions it
comprises: Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd,
and Ssstateen.
Sha is ratified in the RVA23 Profiles Version 1.0 (commit 0273f3c921b6
"rva23/rvb23 ratified") as a new profile-defined extension that captures
the full set of features that are mandated to be supported along with
the H extension.
Extensions Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd,
and Ssstateen are ratified in the RISC-V Profiles Version 1.0 (commit
b1d806605f87 "Updated to ratified state").
The requirement status for Sha and its comprised extension in RISC-V
Profiles are:
- Sha: Mandatory in RVA23S64
- H: Optional in RVA22S64; Mandatory in RVA23S64
- Shcounterenw: Optional in RVA22S64; Mandatory in RVA23S64
- Shgatpa: Optional in RVA22S64; Mandatory in RVA23S64
- Shtvala: Optional in RVA22S64; Mandatory in RVA23S64
- Shvsatpa: Optional in RVA22S64; Mandatory in RVA23S64
- Shvstvala: Optional in RVA22S64; Mandatory in RVA23S64
- Shvstvecd: Optional in RVA22S64; Mandatory in RVA23S64
- Ssstateen: Optional in RVA22S64; Mandatory in RVA23S64
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v4: No change.
v3: Drop dependency check for Sha. Both Sha and the extensions it
implies are allowed to co-exist in DT.
v2: New patch.
---
.../devicetree/bindings/riscv/extensions.yaml | 57 ++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 900270e8d22e..41cb4aeb2667 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -129,6 +129,57 @@ properties:
Document Version 20211203.
# multi-letter extensions, sorted alphanumerically
+ - const: sha
+ description: |
+ The standard Sha extension for augmented hypervisor extension as
+ ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6
+ ("rva23/rvb23 ratified").
+
+ Sha captures the full set of features that are mandated to be
+ supported along with the H extension. Sha comprises the following
+ extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala,
+ Shvstvecd, and Ssstateen.
+
+ - const: shcounterenw
+ description: |
+ The standard Shcounterenw extension for support writable enables
+ in hcounteren for any supported counter, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
+ - const: shgatpa
+ description: |
+ The standard Shgatpa extension indicates that for each supported
+ virtual memory scheme SvNN supported in satp, the corresponding
+ hgatp SvNNx4 mode must be supported. The hgatp mode Bare must
+ also be supported. It is ratified in RISC-V Profiles Version 1.0,
+ with commit b1d806605f87 ("Updated to ratified state.")
+
+ - const: shtvala
+ description: |
+ The standard Shtvala extension for htval be written with the
+ faulting guest physical address in all circumstances permitted by
+ the ISA. It is ratified in RISC-V Profiles Version 1.0, with
+ commit b1d806605f87 ("Updated to ratified state.")
+
+ - const: shvsatpa
+ description: |
+ The standard Shvsatpa extension for vsatp supporting all translation
+ modes supported in satp, as ratified in RISC-V Profiles Version 1.0,
+ with commit b1d806605f87 ("Updated to ratified state.")
+
+ - const: shvstvala
+ description: |
+ The standard Shvstvala extension for vstval provides all needed
+ values as ratified in RISC-V Profiles Version 1.0, with commit
+ b1d806605f87 ("Updated to ratified state.")
+
+ - const: shvstvecd
+ description: |
+ The standard Shvstvecd extension for vstvec supporting Direct mode,
+ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
+ ("Updated to ratified state.")
+
- const: smaia
description: |
The standard Smaia supervisor-level extension for the advanced
@@ -187,6 +238,12 @@ properties:
ratified at commit d70011dde6c2 ("Update to ratified state")
of riscv-j-extension.
+ - const: ssstateen
+ description: |
+ The standard Ssstateen extension for supervisor-mode view of the
+ state-enable extension, as ratified in RISC-V Profiles Version 1.0,
+ with commit b1d806605f87 ("Updated to ratified state.")
+
- const: sstc
description: |
The standard Sstc supervisor-level extension for time compare as
--
2.43.0
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next prev parent reply other threads:[~2026-01-10 5:21 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-10 5:18 [PATCH v4 00/11] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board Guodong Xu
2026-01-10 5:18 ` [PATCH v4 01/11] dt-bindings: riscv: add SpacemiT X100 CPU compatible Guodong Xu
2026-01-14 23:27 ` Paul Walmsley
2026-01-10 5:18 ` [PATCH v4 02/11] dt-bindings: timer: add SpacemiT K3 CLINT Guodong Xu
2026-01-10 5:18 ` [PATCH v4 03/11] dt-bindings: interrupt-controller: add SpacemiT K3 APLIC Guodong Xu
2026-01-10 5:18 ` [PATCH v4 04/11] dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC Guodong Xu
2026-01-10 5:18 ` [PATCH v4 05/11] dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings Guodong Xu
2026-01-10 11:55 ` Yixun Lan
2026-01-12 21:37 ` Conor Dooley
2026-01-10 5:18 ` [PATCH v4 06/11] dt-bindings: riscv: Add B ISA extension description Guodong Xu
2026-01-12 21:41 ` Conor Dooley
2026-01-13 2:44 ` Guodong Xu
2026-01-10 5:18 ` [PATCH v4 07/11] dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm Guodong Xu
2026-01-12 21:38 ` Conor Dooley
2026-01-10 5:18 ` [PATCH v4 08/11] dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl Guodong Xu
2026-01-12 21:39 ` Conor Dooley
2026-01-10 5:18 ` Guodong Xu [this message]
2026-01-12 21:40 ` [PATCH v4 09/11] dt-bindings: riscv: Add Sha and its comprised extensions Conor Dooley
2026-01-10 5:18 ` [PATCH v4 10/11] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC Guodong Xu
2026-01-10 10:00 ` Inochi Amaoto
2026-01-10 11:05 ` Yixun Lan
2026-01-12 8:14 ` Guodong Xu
2026-01-12 7:42 ` Maud Spierings
2026-01-12 7:59 ` Guodong Xu
2026-01-10 5:18 ` [PATCH v4 11/11] riscv: dts: spacemit: add SpacemiT K3 Pico-ITX board device tree Guodong Xu
2026-01-10 9:57 ` Yixun Lan
2026-01-12 8:57 ` Guodong Xu
2026-01-12 21:45 ` [PATCH v4 00/11] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board Conor Dooley
2026-01-13 0:21 ` Yixun Lan
2026-01-13 22:17 ` Conor Dooley
2026-01-14 2:14 ` Yixun Lan
2026-01-14 20:26 ` Rob Herring
2026-01-13 2:51 ` Guodong Xu
2026-01-13 22:25 ` (subset) " Conor Dooley
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