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From: Jason Gunthorpe <jgg@nvidia.com>
To: Vincent Chen <vincent.chen@sifive.com>
Cc: Alexandre Ghiti <alex@ghiti.fr>,
	Albert Ou <aou@eecs.berkeley.edu>,
	iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
	linux-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <pjw@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Tomasz Jeznach <tjeznach@rivosinc.com>,
	Will Deacon <will@kernel.org>,
	lihangjing@bytedance.com, Xu Lu <luxu.kernel@bytedance.com>,
	patches@lists.linux.dev, xieyongji@bytedance.com
Subject: Re: [PATCH v2 0/5] Convert riscv to use the generic iommu page table
Date: Thu, 22 Jan 2026 11:31:34 -0400	[thread overview]
Message-ID: <20260122153134.GO1134360@nvidia.com> (raw)
In-Reply-To: <CABvJ_xiUK9BqUJS9-Sk1sS4vhVhyXN8P8NooZ0t_Zp7ycG0bAw@mail.gmail.com>

On Thu, Jan 22, 2026 at 09:46:47AM +0800, Vincent Chen wrote:
> Hi Jason,
> 
> I tested this patch set on my side with the QEMU-virt machine.
> I used the following QEMU command for testing:
> 
>   $QEMU/qemu-system-riscv64 \
>     -M virt,aia=aplic-imsic,aia-guests=7,iommu-sys=on -m 8G -nographic \
>     -bios $OPENSBI_IMAGE \
>     -serial mon:stdio -serial null -nographic \
>     -device e1000e,netdev=net0 \
>     -netdev user,id=net0 \
>     -cpu rv64,v=true,vlen=256,ssdbltrp=true,smdbltrp=true \
>     -device '{"driver":"virtio-9p-device","fsdev":"share","mount_tag":"host0"}'
> \
>     -fsdev local,id=share,path=share,security_model=mapped \
>     -append 'console=ttyS0 earlycon' \
>     -kernel $KERNEL_IMAGE \
>     -gdb tcp::6234 \
>     -smp 4
> 
> The boot log shows that the e1000e is successfully added to IOMMU group 1:
> 
>   [    0.752808] pci 0000:00:00.0: Adding to iommu group 0
>   [    0.753279] pci 0000:00:01.0: Adding to iommu group 1
>   [...]
>   [    0.763212] e1000e 0000:00:01.0: enabling device (0000 -> 0002)
>   [    0.765241] e1000e 0000:00:01.0: Interrupt Throttling Rate
> (ints/sec) set to dynamic conservative mode
>   [    0.868120] e1000e 0000:00:01.0 eth0: (PCI Express:2.5GT/s:Width
> x1) 52:54:00:12:34:56
>   [    0.868740] e1000e 0000:00:01.0 eth0: Intel(R) PRO/1000 Network Connection
>   [    0.869087] e1000e 0000:00:01.0 eth0: MAC: 3, PHY: 8, PBA No: 000000-000
> 
> In this environment, I used iperf3 to verify that the e1000e functions
> correctly. The result shows that the test completed successfully:

This is great, thanks!

Can you confirm that the iommu was set to translating for this test?

$ cat /sys/kernel/iommu_groups/0/type 
DMA-FQ
$ cat /sys/kernel/iommu_groups/1/type
DMA-FQ

?

Jason

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  reply	other threads:[~2026-01-22 15:31 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-06 15:06 [PATCH v2 0/5] Convert riscv to use the generic iommu page table Jason Gunthorpe
2026-01-06 15:06 ` [PATCH v2 1/5] iommupt: Add the RISC-V page table format Jason Gunthorpe
2026-01-30 19:21   ` Andrew Jones
2026-01-30 23:47     ` Jason Gunthorpe
2026-01-06 15:06 ` [PATCH v2 2/5] iommu/riscv: Disable SADE Jason Gunthorpe
2026-01-06 15:06 ` [PATCH v2 3/5] iommu/riscv: Use the generic iommu page table Jason Gunthorpe
2026-01-06 15:06 ` [PATCH v2 4/5] iommu/riscv: Enable SVNAPOT support for contiguous ptes Jason Gunthorpe
2026-01-06 15:06 ` [PATCH v2 5/5] iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST Jason Gunthorpe
2026-01-30 19:58   ` Andrew Jones
2026-01-30 23:44     ` Jason Gunthorpe
2026-02-04 16:09       ` Andrew Jones
2026-01-22  1:46 ` [PATCH v2 0/5] Convert riscv to use the generic iommu page table Vincent Chen
2026-01-22 15:31   ` Jason Gunthorpe [this message]
2026-01-23  3:05     ` Vincent Chen
2026-01-23 12:29       ` Vincent Chen
2026-01-23 13:52         ` Jason Gunthorpe
2026-01-29 11:21           ` Robin Murphy
2026-01-31  0:27             ` Jason Gunthorpe
2026-02-02 14:00               ` Robin Murphy
2026-02-02 14:37                 ` Jason Gunthorpe
2026-02-02 16:43                   ` Robin Murphy
2026-01-22  7:56 ` Joerg Roedel
2026-01-29  0:46   ` Jason Gunthorpe
2026-01-30 23:14     ` Paul Walmsley
2026-01-31  1:28       ` Tomasz Jeznach

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