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Wed, 04 Mar 2026 16:58:27 -0800 (PST) Received: from inky.localdomain ([2601:647:6700:64d0::5c10]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2be381d5ae9sm1164212eec.26.2026.03.04.16.58.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 16:58:26 -0800 (PST) Date: Wed, 4 Mar 2026 16:58:24 -0800 From: Charlie Jenkins To: Andrew Jones Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Anup Patel , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Conor Dooley , Guodong Xu , Charlie Jenkins , Samuel Holland Subject: Re: [RFC PATCH v1 00/11] riscv: hwprobe: Introduce rva23u64 base behavior Message-ID: <20260305005824.GA132269@inky.localdomain> References: <20260206002349.96740-1-andrew.jones@oss.qualcomm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260206002349.96740-1-andrew.jones@oss.qualcomm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260304_165829_134686_331DD2A6 X-CRM114-Status: GOOD ( 23.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Feb 05, 2026 at 06:23:38PM -0600, Andrew Jones wrote: > Users need a way determine that their harts conform to rva23u64 that > isn't error-prone. While patches 2 and 6 make it possible to determine, > it requires a bunch of probes and checks themselves (see patch9 for the > recipe). This RFC proposes adding an RVA23U64 hwprobe base behavior > (patch8) allowing easy determination. It also proposes adding the bases > to /proc/cpuinfo (patches 10 and 11) -- but those two patches are probably > even more RFCy than the hwprobe proposal... > > The first three patches have been posted previously by their respective > authors and are currently under active review (except patch2 which > appears to have gotten lost in the shuffle). I've collected these > patches into the series since they're necessary for the base and > because I wanted to repost patch2 and patch3 with some changes. patch4 > and patch6 expose more extensions to userspace. patch9 adds a consistency > test for the new hwprobe base behavior bit. Great series! Thanks for pulling these all together, I like this direction. We had dropped patch2 because we were using it for some misaligned access optimizations but then realized that the extension wasn't useful for that so then the patches got lost. In Linux 7.0, patch 1 got applied along with CFI using the first flags of the second key so there is some rebasing to do. I think putting the compatibility info in /proc/cpuinfo is a good idea. There is always hesitance around /proc/cpuinfo because some ill-advised programs try to parse information from it, but it is nice to have an easy way for users to see the compatility and since you also added the hwprobe interface for it this seems reasonable. - Charlie > > Thanks, > drew > > > Andrew Jones (8): > riscv: Add B to hwcap > riscv: hwprobe.rst: Replace tabs with spaces > riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe > riscv: Export have_user_pmlen* booleans > riscv: hwprobe: Introduce rva23u64 base behavior > riscv: selftests: hwprobe: Check rva23u64 consistency > riscv: /proc/cpuinfo: Add rva23 bases to output > riscv: /proc/cpuinfo: Also output rva20 and rva22 isa bases > > Charlie Jenkins (1): > riscv: Standardize extension capitilization > > Jesse Taube (1): > RISC-V: Add Zicclsm to cpufeature and hwprobe > > Paul Walmsley (1): > riscv: hwprobe: add support for RISCV_HWPROBE_KEY_IMA_EXT_1 > > Documentation/arch/riscv/hwprobe.rst | 42 ++- > arch/riscv/include/asm/cpufeature.h | 14 + > arch/riscv/include/asm/hwcap.h | 23 +- > arch/riscv/include/asm/hwprobe.h | 3 +- > arch/riscv/include/asm/switch_to.h | 4 +- > arch/riscv/include/uapi/asm/hwcap.h | 1 + > arch/riscv/include/uapi/asm/hwprobe.h | 9 +- > arch/riscv/kernel/cpu.c | 38 +++ > arch/riscv/kernel/cpufeature.c | 168 ++++++++++-- > arch/riscv/kernel/process.c | 12 +- > arch/riscv/kernel/sys_hwprobe.c | 249 +++++++++++++----- > arch/riscv/kvm/main.c | 2 +- > arch/riscv/kvm/vcpu_fp.c | 28 +- > arch/riscv/kvm/vcpu_onereg.c | 22 +- > arch/riscv/kvm/vcpu_vector.c | 14 +- > .../testing/selftests/riscv/hwprobe/hwprobe.c | 112 +++++++- > .../selftests/riscv/hwprobe/which-cpus.c | 20 +- > 17 files changed, 610 insertions(+), 151 deletions(-) > > -- > 2.43.0 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv