[PATCH net-next v3 09/10] dt-bindings: net: macb: add property indicating timer adjust mode

Conor Dooley
2026-03-10T17:19:45Z

The GEM IP has two methods for modifying the ptp timer. The first of
these, named "increment mode", relies on software controlling the timer
by setting tsu_timer_incr and tsu_timer_incr_sub_nsec and performing
once-off adjustments via the tsu_timer_adjust register. This is what the
macb driver uses. The second mechanism, "timer adjust mode" uses the
gem_tsu_inc_ctrl and gem_tsu_ms signals to control the timer. These
modes are not intended to be used in parallel, but both can be possible
on the same device and which mode is used cannot be determined from the
compatible on all devices, because some users of the GEM IP are SoC
FPGAs that permit configuring how the IP is wired up.

Add a property to indicate that gem_tsu_inc_ctrl and gem_tsu_ms are wired
up for timer adjust mode.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../devicetree/bindings/net/cdns,macb.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml
index a492357570edd..84c32664ccb0d 100644
--- a/Documentation/devicetree/bindings/net/cdns,macb.yaml
+++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml
@@ -139,6 +139,12 @@ properties:
that need to be filled, before the forwarding process is activated.
Width of the SRAM is platform dependent, and can be 4, 8 or 16 bytes.

+ cdns,timer-adjust:
+ type: boolean
+ description:
+ Set when the hardware is operating in timer-adjust mode, where the timer
+ is controlled by the gem_tsu_inc_ctrl and gem_tsu_ms inputs.
+
'#address-cells':
const: 1

@@ -188,6 +194,15 @@ allOf:
properties:
reg:
maxItems: 1
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: microchip,mpfs-macb
+ then:
+ properties:
+ cdns,timer-adjust: false