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Sun, 15 Mar 2026 23:05:43 -0700 (PDT) Received: from m91p.airy.home ([172.92.174.155]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82a07393098sm12525226b3a.62.2026.03.15.23.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Mar 2026 23:05:42 -0700 (PDT) From: Bo Gan To: linux-riscv@lists.infradead.org, samuel.holland@sifive.com, david@redhat.com, palmer@dabbelt.com, pjw@kernel.org, gaohan@iscas.ac.cn, me@ziyao.cc Cc: lizhi2@eswincomputing.com, hal.feng@starfivetech.com, marcel@ziswiler.com, conor@kernel.org, kernel@esmil.dk, devicetree@vger.kernel.org Subject: [RFC PATCH v2 1/3] riscv: alternatives: support auipc+load pair Date: Sun, 15 Mar 2026 23:03:26 -0700 Message-Id: <20260316060328.1173634-2-ganboing@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260316060328.1173634-1-ganboing@gmail.com> References: <20260316060328.1173634-1-ganboing@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260315_230545_903357_43D693E2 X-CRM114-Status: GOOD ( 13.22 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Previously only auipc+jalr pair is supported. Add auipc+load pair to support PC-relative memory load instruction as well. Signed-off-by: Bo Gan --- arch/riscv/include/asm/insn.h | 8 ++++++++ arch/riscv/kernel/alternative.c | 11 ++++++----- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index c3005573e8c99..1c791a8732efc 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -135,6 +135,8 @@ #define RVC_C2_RS1_MASK GENMASK(4, 0) /* parts of opcode for RVG*/ +#define RVG_OPCODE_LOAD 0x03 +#define RVG_OPCODE_STORE 0x23 #define RVG_OPCODE_FENCE 0x0f #define RVG_OPCODE_AUIPC 0x17 #define RVG_OPCODE_BRANCH 0x63 @@ -198,6 +200,8 @@ #define RVG_MATCH_BGE (RV_ENCODE_FUNCT3(BGE) | RVG_OPCODE_BRANCH) #define RVG_MATCH_BLTU (RV_ENCODE_FUNCT3(BLTU) | RVG_OPCODE_BRANCH) #define RVG_MATCH_BGEU (RV_ENCODE_FUNCT3(BGEU) | RVG_OPCODE_BRANCH) +#define RVG_MATCH_LOAD (RVG_OPCODE_LOAD) +#define RVG_MATCH_STORE (RVG_OPCODE_STORE) #define RVG_MATCH_EBREAK (RV_ENCODE_FUNCT12(EBREAK) | RVG_OPCODE_SYSTEM) #define RVG_MATCH_SRET (RV_ENCODE_FUNCT12(SRET) | RVG_OPCODE_SYSTEM) #define RVC_MATCH_C_BEQZ (RVC_ENCODE_FUNCT3(C_BEQZ) | RVC_OPCODE_C1) @@ -222,6 +226,8 @@ #define RVG_MASK_BGE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK) #define RVG_MASK_BLTU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK) #define RVG_MASK_BGEU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK) +#define RVG_MASK_LOAD (RV_INSN_OPCODE_MASK) +#define RVG_MASK_STORE (RV_INSN_OPCODE_MASK) #define RVC_MASK_C_BEQZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK) #define RVC_MASK_C_BNEZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK) #define RVC_MASK_C_EBREAK 0xffff @@ -262,6 +268,8 @@ __RISCV_INSN_FUNCS(c_ebreak, RVC_MASK_C_EBREAK, RVC_MATCH_C_EBREAK) __RISCV_INSN_FUNCS(ebreak, RVG_MASK_EBREAK, RVG_MATCH_EBREAK) __RISCV_INSN_FUNCS(sret, RVG_MASK_SRET, RVG_MATCH_SRET) __RISCV_INSN_FUNCS(fence, RVG_MASK_FENCE, RVG_MATCH_FENCE); +__RISCV_INSN_FUNCS(load, RVG_MASK_LOAD, RVG_MATCH_LOAD); +__RISCV_INSN_FUNCS(store, RVG_MASK_STORE, RVG_MATCH_STORE); /* special case to catch _any_ system instruction */ static __always_inline bool riscv_insn_is_system(u32 code) diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c index 7642704c7f184..04a9d3aed4647 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -74,7 +74,7 @@ static u32 riscv_instruction_at(void *p) return (u32)parcel[0] | (u32)parcel[1] << 16; } -static void riscv_alternative_fix_auipc_jalr(void *ptr, u32 auipc_insn, +static void riscv_alternative_fix_auipc_pair(void *ptr, u32 auipc_insn, u32 jalr_insn, int patch_offset) { u32 call[2] = { auipc_insn, jalr_insn }; @@ -123,14 +123,15 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len, if (riscv_insn_is_auipc(insn) && i < num_insn - 1) { u32 insn2 = riscv_instruction_at(alt_ptr + (i + 1) * sizeof(u32)); - if (!riscv_insn_is_jalr(insn2)) + if (!riscv_insn_is_jalr(insn2) && + !riscv_insn_is_load(insn2)) continue; - /* if instruction pair is a call, it will use the ra register */ - if (RV_EXTRACT_RD_REG(insn) != 1) + if (RV_EXTRACT_RD_REG(insn) != RV_EXTRACT_RS1_REG(insn2)) continue; - riscv_alternative_fix_auipc_jalr(alt_ptr + i * sizeof(u32), + /* insn2 use rd of insn as rs1, patch it */ + riscv_alternative_fix_auipc_pair(alt_ptr + i * sizeof(u32), insn, insn2, patch_offset); i++; } -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv