From: fangyu.yu@linux.alibaba.com
To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca,
kevin.tian@intel.com, baolu.lu@linux.intel.com,
vasant.hegde@amd.com
Cc: guoren@kernel.org, iommu@lists.linux.dev,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Fangyu Yu <fangyu.yu@linux.alibaba.com>
Subject: [PATCH 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt
Date: Sat, 11 Apr 2026 10:22:21 +0800 [thread overview]
Message-ID: <20260411022223.91029-1-fangyu.yu@linux.alibaba.com> (raw)
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
RISC-V Svpbmt adds page-based memory types (PBMT) to PTEs, allowing
mappings to be tagged as e.g. normal memory, non-cacheable memory, or
I/O.
This series wires the RISC-V IOMMU Svpbmt capability into generic_pt
and uses PBMT to encode device memory attributes for IOMMU mappings.
This series builds on top of the new RISC-V IOMMU page table patches:
https://patch.msgid.link/r/0-v3-9dbf0a72a51c+302-iommu_pt_riscv_jgg@nvidia.com
Fangyu Yu (2):
iommu/riscv: Advertise Svpbmt support to generic page table
iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++
drivers/iommu/riscv/iommu.c | 2 ++
include/linux/generic_pt/common.h | 1 +
3 files changed, 12 insertions(+)
--
2.50.1
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next reply other threads:[~2026-04-11 2:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-11 2:22 fangyu.yu [this message]
2026-04-11 2:22 ` [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table fangyu.yu
2026-04-11 12:47 ` Jason Gunthorpe
2026-04-11 16:51 ` Anup Patel
2026-04-12 13:03 ` Guo Ren
2026-04-11 2:22 ` [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits fangyu.yu
2026-04-11 12:47 ` Jason Gunthorpe
2026-04-11 16:51 ` Anup Patel
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