[PATCH 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt

[PATCH 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt

[fangyu.yu]

From: Fangyu Yu <fangyu.yu@linux.alibaba.com>

RISC-V Svpbmt adds page-based memory types (PBMT) to PTEs, allowing
mappings to be tagged as e.g. normal memory, non-cacheable memory, or
I/O.

This series wires the RISC-V IOMMU Svpbmt capability into generic_pt
and uses PBMT to encode device memory attributes for IOMMU mappings.

This series builds on top of the new RISC-V IOMMU page table patches:
https://patch.msgid.link/r/0-v3-9dbf0a72a51c+302-iommu_pt_riscv_jgg@nvidia.com

Fangyu Yu (2):
  iommu/riscv: Advertise Svpbmt support to generic page table
  iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits

 drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++
 drivers/iommu/riscv/iommu.c          | 2 ++
 include/linux/generic_pt/common.h    | 1 +
 3 files changed, 12 insertions(+)

-- 
2.50.1


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[PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table

[fangyu.yu]

From: Fangyu Yu <fangyu.yu@linux.alibaba.com>

The RISC-V IOMMU can optionally support Svpbmt page-based memory types
in its page table format. When present,the generic page table code can
use this capability to encode memory attributes (e.g. MMIO vs normal
memory) in PTEs.

Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
 drivers/iommu/riscv/iommu.c       | 2 ++
 include/linux/generic_pt/common.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index c7d0342aa747..e53883935563 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -1194,6 +1194,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev)
 	cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) |
 			      BIT(PT_FEAT_FLUSH_RANGE) |
 			      BIT(PT_FEAT_RISCV_SVNAPOT_64K);
+	if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT)
+		cfg.common.features |= BIT(PT_FEAT_RISCV_SVPBMT);
 	domain->riscvpt.iommu.nid = dev_to_node(iommu->dev);
 	domain->domain.ops = &riscv_iommu_paging_domain_ops;
 
diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h
index fc5d0b5edadc..dfadf8a5752a 100644
--- a/include/linux/generic_pt/common.h
+++ b/include/linux/generic_pt/common.h
@@ -188,6 +188,7 @@ enum {
 	 * Support the 64k contiguous page size following the Svnapot extension.
 	 */
 	PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START,
+	PT_FEAT_RISCV_SVPBMT,
 
 };
 
-- 
2.50.1


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Re: [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table

[Jason Gunthorpe]

On Sat, Apr 11, 2026 at 10:22:22AM +0800, fangyu.yu@linux.alibaba.com wrote:
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> 
> The RISC-V IOMMU can optionally support Svpbmt page-based memory types
> in its page table format. When present,the generic page table code can
> use this capability to encode memory attributes (e.g. MMIO vs normal
> memory) in PTEs.
> 
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> ---
>  drivers/iommu/riscv/iommu.c       | 2 ++
>  include/linux/generic_pt/common.h | 1 +
>  2 files changed, 3 insertions(+)

Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>

Jason

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Re: [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table

[Anup Patel]

On Sat, Apr 11, 2026 at 7:52 AM <fangyu.yu@linux.alibaba.com> wrote:
>
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
>
> The RISC-V IOMMU can optionally support Svpbmt page-based memory types
> in its page table format. When present,the generic page table code can
> use this capability to encode memory attributes (e.g. MMIO vs normal
> memory) in PTEs.
>
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>

Looks good from RISC-V perspective.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup


> ---
>  drivers/iommu/riscv/iommu.c       | 2 ++
>  include/linux/generic_pt/common.h | 1 +
>  2 files changed, 3 insertions(+)
>
> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
> index c7d0342aa747..e53883935563 100644
> --- a/drivers/iommu/riscv/iommu.c
> +++ b/drivers/iommu/riscv/iommu.c
> @@ -1194,6 +1194,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev)
>         cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) |
>                               BIT(PT_FEAT_FLUSH_RANGE) |
>                               BIT(PT_FEAT_RISCV_SVNAPOT_64K);
> +       if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT)
> +               cfg.common.features |= BIT(PT_FEAT_RISCV_SVPBMT);
>         domain->riscvpt.iommu.nid = dev_to_node(iommu->dev);
>         domain->domain.ops = &riscv_iommu_paging_domain_ops;
>
> diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h
> index fc5d0b5edadc..dfadf8a5752a 100644
> --- a/include/linux/generic_pt/common.h
> +++ b/include/linux/generic_pt/common.h
> @@ -188,6 +188,7 @@ enum {
>          * Support the 64k contiguous page size following the Svnapot extension.
>          */
>         PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START,
> +       PT_FEAT_RISCV_SVPBMT,
>
>  };
>
> --
> 2.50.1
>
>

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Re: [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table

[Guo Ren]

On Sat, Apr 11, 2026 at 10:22 AM <fangyu.yu@linux.alibaba.com> wrote:
>
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
>
> The RISC-V IOMMU can optionally support Svpbmt page-based memory types
> in its page table format. When present,the generic page table code can
> use this capability to encode memory attributes (e.g. MMIO vs normal
> memory) in PTEs.
>
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> ---
>  drivers/iommu/riscv/iommu.c       | 2 ++
>  include/linux/generic_pt/common.h | 1 +
>  2 files changed, 3 insertions(+)
>
> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
> index c7d0342aa747..e53883935563 100644
> --- a/drivers/iommu/riscv/iommu.c
> +++ b/drivers/iommu/riscv/iommu.c
> @@ -1194,6 +1194,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev)
>         cfg. common.features = BIT(PT_FEAT_SIGN_EXTEND) |
>                               BIT(PT_FEAT_FLUSH_RANGE) |
>                               BIT(PT_FEAT_RISCV_SVNAPOT_64K);
> +       if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT)
> +               cfg.common.features |= BIT(PT_FEAT_RISCV_SVPBMT);
>         domain->riscvpt.iommu.nid = dev_to_node(iommu->dev);
>         domain->domain.ops = &riscv_iommu_paging_domain_ops;
>
> diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h
> index fc5d0b5edadc..dfadf8a5752a 100644
> --- a/include/linux/generic_pt/common.h
> +++ b/include/linux/generic_pt/common.h
> @@ -188,6 +188,7 @@ enum {
>          * Support the 64k contiguous page size following the Svnapot extension.
>          */
>         PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START,
> +       PT_FEAT_RISCV_SVPBMT,
>
>  };
>
> --
> 2.50.1
>

Reviewed-by: Guo Ren <guoren@kernel.org>


--
Best Regards
 Guo Ren

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Re: [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table

[Nutty.Liu]

On 4/11/2026 10:22 AM, fangyu.yu@linux.alibaba.com wrote:
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
>
> The RISC-V IOMMU can optionally support Svpbmt page-based memory types
> in its page table format. When present,the generic page table code can
> use this capability to encode memory attributes (e.g. MMIO vs normal
> memory) in PTEs.
>
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> ---
>   drivers/iommu/riscv/iommu.c       | 2 ++
>   include/linux/generic_pt/common.h | 1 +
>   2 files changed, 3 insertions(+)
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>

Thanks,
Nutty

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RE: [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table

[Tian, Kevin]

> From: fangyu.yu@linux.alibaba.com <fangyu.yu@linux.alibaba.com>
> Sent: Saturday, April 11, 2026 10:22 AM
> 
> diff --git a/include/linux/generic_pt/common.h
> b/include/linux/generic_pt/common.h
> index fc5d0b5edadc..dfadf8a5752a 100644
> --- a/include/linux/generic_pt/common.h
> +++ b/include/linux/generic_pt/common.h
> @@ -188,6 +188,7 @@ enum {
>  	 * Support the 64k contiguous page size following the Svnapot
> extension.
>  	 */
>  	PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START,
> +	PT_FEAT_RISCV_SVPBMT,
> 

nit - every feature has a comment.

Reviewed-by: Kevin Tian <kevin.tian@intel.com>

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Re: RE: [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table

[fangyu.yu]

>> From: fangyu.yu@linux.alibaba.com <fangyu.yu@linux.alibaba.com>
>> Sent: Saturday, April 11, 2026 10:22 AM
>>
>> diff --git a/include/linux/generic_pt/common.h
>> b/include/linux/generic_pt/common.h
>> index fc5d0b5edadc..dfadf8a5752a 100644
>> --- a/include/linux/generic_pt/common.h
>> +++ b/include/linux/generic_pt/common.h
>> @@ -188,6 +188,7 @@ enum {
>>  	 * Support the 64k contiguous page size following the Svnapot
>> extension.
>>  	 */
>>  	PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START,
>> +	PT_FEAT_RISCV_SVPBMT,
>>
>
>nit - every feature has a comment.

Thanks Kevin.
I'll add a comment for PT_FEAT_RISCV_SVPBMT in the next revision.

Fangyu,
Thanks
>
>Reviewed-by: Kevin Tian <kevin.tian@intel.com>

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Re: [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table

[Jason Gunthorpe]

On Mon, Apr 13, 2026 at 06:45:07AM +0000, Tian, Kevin wrote:
> > From: fangyu.yu@linux.alibaba.com <fangyu.yu@linux.alibaba.com>
> > Sent: Saturday, April 11, 2026 10:22 AM
> > 
> > diff --git a/include/linux/generic_pt/common.h
> > b/include/linux/generic_pt/common.h
> > index fc5d0b5edadc..dfadf8a5752a 100644
> > --- a/include/linux/generic_pt/common.h
> > +++ b/include/linux/generic_pt/common.h
> > @@ -188,6 +188,7 @@ enum {
> >  	 * Support the 64k contiguous page size following the Svnapot
> > extension.
> >  	 */
> >  	PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START,
> > +	PT_FEAT_RISCV_SVPBMT,
> > 
> 
> nit - every feature has a comment.
> 
> Reviewed-by: Kevin Tian <kevin.tian@intel.com>

Oh that's right, please add a good comment!

Jason

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[PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits

[fangyu.yu]

From: Fangyu Yu <fangyu.yu@linux.alibaba.com>

When the RISC-V IOMMU page table format support Svpbmt, PBMT provides
a way to tag mappings with page-based memory types. Encode memory type
via PBMT in RISC-V IOMMU PTEs:

  - IOMMU_MMIO   -> PBMT=IO
  - !IOMMU_CACHE -> PBMT=NC
  - otherwise    -> PBMT=Normal (PBMT=0)

Clear the PBMT field before applying the selected encoding, and only
touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised.

Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
 drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h
index a7fef6266a36..02051bb3c6e5 100644
--- a/drivers/iommu/generic_pt/fmt/riscv.h
+++ b/drivers/iommu/generic_pt/fmt/riscv.h
@@ -58,6 +58,8 @@ enum {
 	RISCVPT_G = BIT(5),
 	RISCVPT_A = BIT(6),
 	RISCVPT_D = BIT(7),
+	RISCVPT_NC = BIT(61),
+	RISCVPT_IO = BIT(62),
 	RISCVPT_RSW = GENMASK(9, 8),
 	RISCVPT_PPN32 = GENMASK(31, 10),
 
@@ -237,6 +239,13 @@ static inline int riscvpt_iommu_set_prot(struct pt_common *common,
 		pte |= RISCVPT_R;
 	if (!(iommu_prot & IOMMU_NOEXEC))
 		pte |= RISCVPT_X;
+	if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) {
+		pte &= ~RISCVPT_PBMT;
+		if (iommu_prot & IOMMU_MMIO)
+			pte |= RISCVPT_IO;
+		else if (!(iommu_prot & IOMMU_CACHE))
+			pte |= RISCVPT_NC;
+	}
 
 	/* Caller must specify a supported combination of flags */
 	if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) == 0))
-- 
2.50.1


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Re: [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits

[Jason Gunthorpe]

On Sat, Apr 11, 2026 at 10:22:23AM +0800, fangyu.yu@linux.alibaba.com wrote:
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> 
> When the RISC-V IOMMU page table format support Svpbmt, PBMT provides
> a way to tag mappings with page-based memory types. Encode memory type
> via PBMT in RISC-V IOMMU PTEs:
> 
>   - IOMMU_MMIO   -> PBMT=IO
>   - !IOMMU_CACHE -> PBMT=NC
>   - otherwise    -> PBMT=Normal (PBMT=0)
> 
> Clear the PBMT field before applying the selected encoding, and only
> touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised.
> 
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> ---
>  drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++
>  1 file changed, 9 insertions(+)

Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>

This is similar to ARM now with the 3 kinds..

Jason

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Re: [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits

[Anup Patel]

On Sat, Apr 11, 2026 at 7:52 AM <fangyu.yu@linux.alibaba.com> wrote:
>
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
>
> When the RISC-V IOMMU page table format support Svpbmt, PBMT provides
> a way to tag mappings with page-based memory types. Encode memory type
> via PBMT in RISC-V IOMMU PTEs:
>
>   - IOMMU_MMIO   -> PBMT=IO
>   - !IOMMU_CACHE -> PBMT=NC
>   - otherwise    -> PBMT=Normal (PBMT=0)
>
> Clear the PBMT field before applying the selected encoding, and only
> touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised.
>
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>

Looks good from RISC-V perspective.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup


> ---
>  drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h
> index a7fef6266a36..02051bb3c6e5 100644
> --- a/drivers/iommu/generic_pt/fmt/riscv.h
> +++ b/drivers/iommu/generic_pt/fmt/riscv.h
> @@ -58,6 +58,8 @@ enum {
>         RISCVPT_G = BIT(5),
>         RISCVPT_A = BIT(6),
>         RISCVPT_D = BIT(7),
> +       RISCVPT_NC = BIT(61),
> +       RISCVPT_IO = BIT(62),
>         RISCVPT_RSW = GENMASK(9, 8),
>         RISCVPT_PPN32 = GENMASK(31, 10),
>
> @@ -237,6 +239,13 @@ static inline int riscvpt_iommu_set_prot(struct pt_common *common,
>                 pte |= RISCVPT_R;
>         if (!(iommu_prot & IOMMU_NOEXEC))
>                 pte |= RISCVPT_X;
> +       if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) {
> +               pte &= ~RISCVPT_PBMT;
> +               if (iommu_prot & IOMMU_MMIO)
> +                       pte |= RISCVPT_IO;
> +               else if (!(iommu_prot & IOMMU_CACHE))
> +                       pte |= RISCVPT_NC;
> +       }
>
>         /* Caller must specify a supported combination of flags */
>         if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) == 0))
> --
> 2.50.1
>
>

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Re: [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits

[Guo Ren]

On Sat, Apr 11, 2026 at 10:22 AM <fangyu.yu@linux.alibaba.com> wrote:
>
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
>
> When the RISC-V IOMMU page table format support Svpbmt, PBMT provides
> a way to tag mappings with page-based memory types. Encode memory type
> via PBMT in RISC-V IOMMU PTEs:
>
>   - IOMMU_MMIO   -> PBMT=IO
>   - !IOMMU_CACHE -> PBMT=NC
>   - otherwise    -> PBMT=Normal (PBMT=0)
>
> Clear the PBMT field before applying the selected encoding, and only
> touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised.
>
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> ---
>  drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h
> index a7fef6266a36..02051bb3c6e5 100644
> --- a/drivers/iommu/generic_pt/fmt/riscv.h
> +++ b/drivers/iommu/generic_pt/fmt/riscv.h
> @@ -58,6 +58,8 @@ enum {
>         RISCVPT_G = BIT(5),
>         RISCVPT_A = BIT(6),
>         RISCVPT_D = BIT(7),
> +       RISCVPT_NC = BIT(61),
> +       RISCVPT_IO = BIT(62),
>         RISCVPT_RSW = GENMASK(9, 8),
>         RISCVPT_PPN32 = GENMASK(31, 10),
>
> @@ -237,6 +239,13 @@ static inline int riscvpt_iommu_set_prot(struct pt_common *common,
>                 pte |= RISCVPT_R;
>         if (!(iommu_prot & IOMMU_NOEXEC))
>                 pte |= RISCVPT_X;
> +       if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) {
> +               pte &= ~RISCVPT_PBMT;
> +               if (iommu_prot & IOMMU_MMIO)
> +                       pte |= RISCVPT_IO;
> +               else if (!(iommu_prot & IOMMU_CACHE))
> +                       pte |= RISCVPT_NC;
> +       }
>
>         /* Caller must specify a supported combination of flags */
>         if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) == 0))
> --
> 2.50.1
>
I'm okay with the current way of  MMIO & CACHE mapping to IO & NC.

Reviewed-by: Guo Ren <guoren@kernel.org>

-- 
Best Regards
 Guo Ren

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Re: [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits

[Nutty.Liu]

On 4/11/2026 10:22 AM, fangyu.yu@linux.alibaba.com wrote:
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
>
> When the RISC-V IOMMU page table format support Svpbmt, PBMT provides
> a way to tag mappings with page-based memory types. Encode memory type
> via PBMT in RISC-V IOMMU PTEs:
>
>    - IOMMU_MMIO   -> PBMT=IO
>    - !IOMMU_CACHE -> PBMT=NC
>    - otherwise    -> PBMT=Normal (PBMT=0)
>
> Clear the PBMT field before applying the selected encoding, and only
> touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised.
>
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> ---
>   drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++
>   1 file changed, 9 insertions(+)
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>

Thanks,
Nutty

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RE: [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits

[Tian, Kevin]

> From: fangyu.yu@linux.alibaba.com <fangyu.yu@linux.alibaba.com>
> Sent: Saturday, April 11, 2026 10:22 AM
> 
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> 
> When the RISC-V IOMMU page table format support Svpbmt, PBMT provides
> a way to tag mappings with page-based memory types. Encode memory type
> via PBMT in RISC-V IOMMU PTEs:
> 
>   - IOMMU_MMIO   -> PBMT=IO
>   - !IOMMU_CACHE -> PBMT=NC

In concept IOMMU_CACHE is cleared when IOMMU_MMIO is set. From the
code PBMT=IO in this case.

So strictly speaking the 2nd line should be:

  - !IOMMU_MMIO && !IOMMU_CACHE -> PBMT=NC

??

>   - otherwise    -> PBMT=Normal (PBMT=0)
> 
> Clear the PBMT field before applying the selected encoding, and only
> touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised.
> 
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> ---
>  drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/iommu/generic_pt/fmt/riscv.h
> b/drivers/iommu/generic_pt/fmt/riscv.h
> index a7fef6266a36..02051bb3c6e5 100644
> --- a/drivers/iommu/generic_pt/fmt/riscv.h
> +++ b/drivers/iommu/generic_pt/fmt/riscv.h
> @@ -58,6 +58,8 @@ enum {
>  	RISCVPT_G = BIT(5),
>  	RISCVPT_A = BIT(6),
>  	RISCVPT_D = BIT(7),
> +	RISCVPT_NC = BIT(61),
> +	RISCVPT_IO = BIT(62),
>  	RISCVPT_RSW = GENMASK(9, 8),
>  	RISCVPT_PPN32 = GENMASK(31, 10),

sort by bit positions

> 
> @@ -237,6 +239,13 @@ static inline int riscvpt_iommu_set_prot(struct
> pt_common *common,
>  		pte |= RISCVPT_R;
>  	if (!(iommu_prot & IOMMU_NOEXEC))
>  		pte |= RISCVPT_X;
> +	if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) {
> +		pte &= ~RISCVPT_PBMT;

this is unnecessary due to the earlier assignment:

	pte = RISCVPT_A | RISCVPT_U;

> +		if (iommu_prot & IOMMU_MMIO)
> +			pte |= RISCVPT_IO;
> +		else if (!(iommu_prot & IOMMU_CACHE))
> +			pte |= RISCVPT_NC;
> +	}
> 
>  	/* Caller must specify a supported combination of flags */
>  	if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) == 0))
> --
> 2.50.1


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Re: RE: [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits

[fangyu.yu]

>> From: fangyu.yu@linux.alibaba.com <fangyu.yu@linux.alibaba.com>
>> Sent: Saturday, April 11, 2026 10:22 AM
>>
>> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
>>
>> When the RISC-V IOMMU page table format support Svpbmt, PBMT provides
>> a way to tag mappings with page-based memory types. Encode memory type
>> via PBMT in RISC-V IOMMU PTEs:
>>
>>   - IOMMU_MMIO   -> PBMT=IO
>>   - !IOMMU_CACHE -> PBMT=NC
>
>In concept IOMMU_CACHE is cleared when IOMMU_MMIO is set. From the
>code PBMT=IO in this case.
>
>So strictly speaking the 2nd line should be:
>
>  - !IOMMU_MMIO && !IOMMU_CACHE -> PBMT=NC
>
>??
>

Agree. I'll clarify the commit message accordingly to avoid implying
that the MMIO case could fall into the NC rule.

>>   - otherwise    -> PBMT=Normal (PBMT=0)
>>
>> Clear the PBMT field before applying the selected encoding, and only
>> touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised.
>>
>> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
>> ---
>>  drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/drivers/iommu/generic_pt/fmt/riscv.h
>> b/drivers/iommu/generic_pt/fmt/riscv.h
>> index a7fef6266a36..02051bb3c6e5 100644
>> --- a/drivers/iommu/generic_pt/fmt/riscv.h
>> +++ b/drivers/iommu/generic_pt/fmt/riscv.h
>> @@ -58,6 +58,8 @@ enum {
>>  	RISCVPT_G = BIT(5),
>>  	RISCVPT_A = BIT(6),
>>  	RISCVPT_D = BIT(7),
>> +	RISCVPT_NC = BIT(61),
>> +	RISCVPT_IO = BIT(62),
>>  	RISCVPT_RSW = GENMASK(9, 8),
>>  	RISCVPT_PPN32 = GENMASK(31, 10),
>
>sort by bit positions
>

Got it, will reorder in v2.

>>
>> @@ -237,6 +239,13 @@ static inline int riscvpt_iommu_set_prot(struct
>> pt_common *common,
>>  		pte |= RISCVPT_R;
>>  	if (!(iommu_prot & IOMMU_NOEXEC))
>>  		pte |= RISCVPT_X;
>> +	if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) {
>> +		pte &= ~RISCVPT_PBMT;
>
>this is unnecessary due to the earlier assignment:
>
>	pte = RISCVPT_A | RISCVPT_U;
>

As things stand it’s not needed, I'll drop it in v2.

>> +		if (iommu_prot & IOMMU_MMIO)
>> +			pte |= RISCVPT_IO;
>> +		else if (!(iommu_prot & IOMMU_CACHE))
>> +			pte |= RISCVPT_NC;
>> +	}
>>
>>  	/* Caller must specify a supported combination of flags */
>>  	if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) == 0))
>> --
>> 2.50.1

Thanks,
Fangyu

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