* [PATCH 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt @ 2026-04-11 2:22 fangyu.yu 2026-04-11 2:22 ` [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table fangyu.yu 2026-04-11 2:22 ` [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits fangyu.yu 0 siblings, 2 replies; 9+ messages in thread From: fangyu.yu @ 2026-04-11 2:22 UTC (permalink / raw) To: joro, will, robin.murphy, pjw, palmer, aou, alex, tjeznach, jgg, kevin.tian, baolu.lu, vasant.hegde Cc: guoren, iommu, kvm-riscv, linux-riscv, linux-kernel, Fangyu Yu From: Fangyu Yu <fangyu.yu@linux.alibaba.com> RISC-V Svpbmt adds page-based memory types (PBMT) to PTEs, allowing mappings to be tagged as e.g. normal memory, non-cacheable memory, or I/O. This series wires the RISC-V IOMMU Svpbmt capability into generic_pt and uses PBMT to encode device memory attributes for IOMMU mappings. This series builds on top of the new RISC-V IOMMU page table patches: https://patch.msgid.link/r/0-v3-9dbf0a72a51c+302-iommu_pt_riscv_jgg@nvidia.com Fangyu Yu (2): iommu/riscv: Advertise Svpbmt support to generic page table iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++ drivers/iommu/riscv/iommu.c | 2 ++ include/linux/generic_pt/common.h | 1 + 3 files changed, 12 insertions(+) -- 2.50.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table 2026-04-11 2:22 [PATCH 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt fangyu.yu @ 2026-04-11 2:22 ` fangyu.yu 2026-04-11 12:47 ` Jason Gunthorpe ` (2 more replies) 2026-04-11 2:22 ` [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits fangyu.yu 1 sibling, 3 replies; 9+ messages in thread From: fangyu.yu @ 2026-04-11 2:22 UTC (permalink / raw) To: joro, will, robin.murphy, pjw, palmer, aou, alex, tjeznach, jgg, kevin.tian, baolu.lu, vasant.hegde Cc: guoren, iommu, kvm-riscv, linux-riscv, linux-kernel, Fangyu Yu From: Fangyu Yu <fangyu.yu@linux.alibaba.com> The RISC-V IOMMU can optionally support Svpbmt page-based memory types in its page table format. When present,the generic page table code can use this capability to encode memory attributes (e.g. MMIO vs normal memory) in PTEs. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> --- drivers/iommu/riscv/iommu.c | 2 ++ include/linux/generic_pt/common.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index c7d0342aa747..e53883935563 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1194,6 +1194,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev) cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) | BIT(PT_FEAT_FLUSH_RANGE) | BIT(PT_FEAT_RISCV_SVNAPOT_64K); + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT) + cfg.common.features |= BIT(PT_FEAT_RISCV_SVPBMT); domain->riscvpt.iommu.nid = dev_to_node(iommu->dev); domain->domain.ops = &riscv_iommu_paging_domain_ops; diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h index fc5d0b5edadc..dfadf8a5752a 100644 --- a/include/linux/generic_pt/common.h +++ b/include/linux/generic_pt/common.h @@ -188,6 +188,7 @@ enum { * Support the 64k contiguous page size following the Svnapot extension. */ PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START, + PT_FEAT_RISCV_SVPBMT, }; -- 2.50.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table 2026-04-11 2:22 ` [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table fangyu.yu @ 2026-04-11 12:47 ` Jason Gunthorpe 2026-04-11 16:51 ` Anup Patel 2026-04-12 13:03 ` Guo Ren 2 siblings, 0 replies; 9+ messages in thread From: Jason Gunthorpe @ 2026-04-11 12:47 UTC (permalink / raw) To: fangyu.yu Cc: joro, will, robin.murphy, pjw, palmer, aou, alex, tjeznach, kevin.tian, baolu.lu, vasant.hegde, guoren, iommu, kvm-riscv, linux-riscv, linux-kernel On Sat, Apr 11, 2026 at 10:22:22AM +0800, fangyu.yu@linux.alibaba.com wrote: > From: Fangyu Yu <fangyu.yu@linux.alibaba.com> > > The RISC-V IOMMU can optionally support Svpbmt page-based memory types > in its page table format. When present,the generic page table code can > use this capability to encode memory attributes (e.g. MMIO vs normal > memory) in PTEs. > > Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> > --- > drivers/iommu/riscv/iommu.c | 2 ++ > include/linux/generic_pt/common.h | 1 + > 2 files changed, 3 insertions(+) Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Jason _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table 2026-04-11 2:22 ` [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table fangyu.yu 2026-04-11 12:47 ` Jason Gunthorpe @ 2026-04-11 16:51 ` Anup Patel 2026-04-12 13:03 ` Guo Ren 2 siblings, 0 replies; 9+ messages in thread From: Anup Patel @ 2026-04-11 16:51 UTC (permalink / raw) To: fangyu.yu Cc: joro, will, robin.murphy, pjw, palmer, aou, alex, tjeznach, jgg, kevin.tian, baolu.lu, vasant.hegde, guoren, iommu, kvm-riscv, linux-riscv, linux-kernel On Sat, Apr 11, 2026 at 7:52 AM <fangyu.yu@linux.alibaba.com> wrote: > > From: Fangyu Yu <fangyu.yu@linux.alibaba.com> > > The RISC-V IOMMU can optionally support Svpbmt page-based memory types > in its page table format. When present,the generic page table code can > use this capability to encode memory attributes (e.g. MMIO vs normal > memory) in PTEs. > > Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Looks good from RISC-V perspective. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > drivers/iommu/riscv/iommu.c | 2 ++ > include/linux/generic_pt/common.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c > index c7d0342aa747..e53883935563 100644 > --- a/drivers/iommu/riscv/iommu.c > +++ b/drivers/iommu/riscv/iommu.c > @@ -1194,6 +1194,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev) > cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) | > BIT(PT_FEAT_FLUSH_RANGE) | > BIT(PT_FEAT_RISCV_SVNAPOT_64K); > + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT) > + cfg.common.features |= BIT(PT_FEAT_RISCV_SVPBMT); > domain->riscvpt.iommu.nid = dev_to_node(iommu->dev); > domain->domain.ops = &riscv_iommu_paging_domain_ops; > > diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h > index fc5d0b5edadc..dfadf8a5752a 100644 > --- a/include/linux/generic_pt/common.h > +++ b/include/linux/generic_pt/common.h > @@ -188,6 +188,7 @@ enum { > * Support the 64k contiguous page size following the Svnapot extension. > */ > PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START, > + PT_FEAT_RISCV_SVPBMT, > > }; > > -- > 2.50.1 > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table 2026-04-11 2:22 ` [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table fangyu.yu 2026-04-11 12:47 ` Jason Gunthorpe 2026-04-11 16:51 ` Anup Patel @ 2026-04-12 13:03 ` Guo Ren 2 siblings, 0 replies; 9+ messages in thread From: Guo Ren @ 2026-04-12 13:03 UTC (permalink / raw) To: fangyu.yu Cc: joro, will, robin.murphy, pjw, palmer, aou, alex, tjeznach, jgg, kevin.tian, baolu.lu, vasant.hegde, iommu, kvm-riscv, linux-riscv, linux-kernel On Sat, Apr 11, 2026 at 10:22 AM <fangyu.yu@linux.alibaba.com> wrote: > > From: Fangyu Yu <fangyu.yu@linux.alibaba.com> > > The RISC-V IOMMU can optionally support Svpbmt page-based memory types > in its page table format. When present,the generic page table code can > use this capability to encode memory attributes (e.g. MMIO vs normal > memory) in PTEs. > > Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> > --- > drivers/iommu/riscv/iommu.c | 2 ++ > include/linux/generic_pt/common.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c > index c7d0342aa747..e53883935563 100644 > --- a/drivers/iommu/riscv/iommu.c > +++ b/drivers/iommu/riscv/iommu.c > @@ -1194,6 +1194,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev) > cfg. common.features = BIT(PT_FEAT_SIGN_EXTEND) | > BIT(PT_FEAT_FLUSH_RANGE) | > BIT(PT_FEAT_RISCV_SVNAPOT_64K); > + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT) > + cfg.common.features |= BIT(PT_FEAT_RISCV_SVPBMT); > domain->riscvpt.iommu.nid = dev_to_node(iommu->dev); > domain->domain.ops = &riscv_iommu_paging_domain_ops; > > diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h > index fc5d0b5edadc..dfadf8a5752a 100644 > --- a/include/linux/generic_pt/common.h > +++ b/include/linux/generic_pt/common.h > @@ -188,6 +188,7 @@ enum { > * Support the 64k contiguous page size following the Svnapot extension. > */ > PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START, > + PT_FEAT_RISCV_SVPBMT, > > }; > > -- > 2.50.1 > Reviewed-by: Guo Ren <guoren@kernel.org> -- Best Regards Guo Ren _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits 2026-04-11 2:22 [PATCH 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt fangyu.yu 2026-04-11 2:22 ` [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table fangyu.yu @ 2026-04-11 2:22 ` fangyu.yu 2026-04-11 12:47 ` Jason Gunthorpe ` (2 more replies) 1 sibling, 3 replies; 9+ messages in thread From: fangyu.yu @ 2026-04-11 2:22 UTC (permalink / raw) To: joro, will, robin.murphy, pjw, palmer, aou, alex, tjeznach, jgg, kevin.tian, baolu.lu, vasant.hegde Cc: guoren, iommu, kvm-riscv, linux-riscv, linux-kernel, Fangyu Yu From: Fangyu Yu <fangyu.yu@linux.alibaba.com> When the RISC-V IOMMU page table format support Svpbmt, PBMT provides a way to tag mappings with page-based memory types. Encode memory type via PBMT in RISC-V IOMMU PTEs: - IOMMU_MMIO -> PBMT=IO - !IOMMU_CACHE -> PBMT=NC - otherwise -> PBMT=Normal (PBMT=0) Clear the PBMT field before applying the selected encoding, and only touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised. Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> --- drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h index a7fef6266a36..02051bb3c6e5 100644 --- a/drivers/iommu/generic_pt/fmt/riscv.h +++ b/drivers/iommu/generic_pt/fmt/riscv.h @@ -58,6 +58,8 @@ enum { RISCVPT_G = BIT(5), RISCVPT_A = BIT(6), RISCVPT_D = BIT(7), + RISCVPT_NC = BIT(61), + RISCVPT_IO = BIT(62), RISCVPT_RSW = GENMASK(9, 8), RISCVPT_PPN32 = GENMASK(31, 10), @@ -237,6 +239,13 @@ static inline int riscvpt_iommu_set_prot(struct pt_common *common, pte |= RISCVPT_R; if (!(iommu_prot & IOMMU_NOEXEC)) pte |= RISCVPT_X; + if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) { + pte &= ~RISCVPT_PBMT; + if (iommu_prot & IOMMU_MMIO) + pte |= RISCVPT_IO; + else if (!(iommu_prot & IOMMU_CACHE)) + pte |= RISCVPT_NC; + } /* Caller must specify a supported combination of flags */ if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) == 0)) -- 2.50.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits 2026-04-11 2:22 ` [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits fangyu.yu @ 2026-04-11 12:47 ` Jason Gunthorpe 2026-04-11 16:51 ` Anup Patel 2026-04-12 14:08 ` Guo Ren 2 siblings, 0 replies; 9+ messages in thread From: Jason Gunthorpe @ 2026-04-11 12:47 UTC (permalink / raw) To: fangyu.yu Cc: joro, will, robin.murphy, pjw, palmer, aou, alex, tjeznach, kevin.tian, baolu.lu, vasant.hegde, guoren, iommu, kvm-riscv, linux-riscv, linux-kernel On Sat, Apr 11, 2026 at 10:22:23AM +0800, fangyu.yu@linux.alibaba.com wrote: > From: Fangyu Yu <fangyu.yu@linux.alibaba.com> > > When the RISC-V IOMMU page table format support Svpbmt, PBMT provides > a way to tag mappings with page-based memory types. Encode memory type > via PBMT in RISC-V IOMMU PTEs: > > - IOMMU_MMIO -> PBMT=IO > - !IOMMU_CACHE -> PBMT=NC > - otherwise -> PBMT=Normal (PBMT=0) > > Clear the PBMT field before applying the selected encoding, and only > touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised. > > Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> > --- > drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++ > 1 file changed, 9 insertions(+) Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> This is similar to ARM now with the 3 kinds.. Jason _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits 2026-04-11 2:22 ` [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits fangyu.yu 2026-04-11 12:47 ` Jason Gunthorpe @ 2026-04-11 16:51 ` Anup Patel 2026-04-12 14:08 ` Guo Ren 2 siblings, 0 replies; 9+ messages in thread From: Anup Patel @ 2026-04-11 16:51 UTC (permalink / raw) To: fangyu.yu Cc: joro, will, robin.murphy, pjw, palmer, aou, alex, tjeznach, jgg, kevin.tian, baolu.lu, vasant.hegde, guoren, iommu, kvm-riscv, linux-riscv, linux-kernel On Sat, Apr 11, 2026 at 7:52 AM <fangyu.yu@linux.alibaba.com> wrote: > > From: Fangyu Yu <fangyu.yu@linux.alibaba.com> > > When the RISC-V IOMMU page table format support Svpbmt, PBMT provides > a way to tag mappings with page-based memory types. Encode memory type > via PBMT in RISC-V IOMMU PTEs: > > - IOMMU_MMIO -> PBMT=IO > - !IOMMU_CACHE -> PBMT=NC > - otherwise -> PBMT=Normal (PBMT=0) > > Clear the PBMT field before applying the selected encoding, and only > touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised. > > Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Looks good from RISC-V perspective. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h > index a7fef6266a36..02051bb3c6e5 100644 > --- a/drivers/iommu/generic_pt/fmt/riscv.h > +++ b/drivers/iommu/generic_pt/fmt/riscv.h > @@ -58,6 +58,8 @@ enum { > RISCVPT_G = BIT(5), > RISCVPT_A = BIT(6), > RISCVPT_D = BIT(7), > + RISCVPT_NC = BIT(61), > + RISCVPT_IO = BIT(62), > RISCVPT_RSW = GENMASK(9, 8), > RISCVPT_PPN32 = GENMASK(31, 10), > > @@ -237,6 +239,13 @@ static inline int riscvpt_iommu_set_prot(struct pt_common *common, > pte |= RISCVPT_R; > if (!(iommu_prot & IOMMU_NOEXEC)) > pte |= RISCVPT_X; > + if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) { > + pte &= ~RISCVPT_PBMT; > + if (iommu_prot & IOMMU_MMIO) > + pte |= RISCVPT_IO; > + else if (!(iommu_prot & IOMMU_CACHE)) > + pte |= RISCVPT_NC; > + } > > /* Caller must specify a supported combination of flags */ > if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) == 0)) > -- > 2.50.1 > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits 2026-04-11 2:22 ` [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits fangyu.yu 2026-04-11 12:47 ` Jason Gunthorpe 2026-04-11 16:51 ` Anup Patel @ 2026-04-12 14:08 ` Guo Ren 2 siblings, 0 replies; 9+ messages in thread From: Guo Ren @ 2026-04-12 14:08 UTC (permalink / raw) To: fangyu.yu Cc: joro, will, robin.murphy, pjw, palmer, aou, alex, tjeznach, jgg, kevin.tian, baolu.lu, vasant.hegde, iommu, kvm-riscv, linux-riscv, linux-kernel On Sat, Apr 11, 2026 at 10:22 AM <fangyu.yu@linux.alibaba.com> wrote: > > From: Fangyu Yu <fangyu.yu@linux.alibaba.com> > > When the RISC-V IOMMU page table format support Svpbmt, PBMT provides > a way to tag mappings with page-based memory types. Encode memory type > via PBMT in RISC-V IOMMU PTEs: > > - IOMMU_MMIO -> PBMT=IO > - !IOMMU_CACHE -> PBMT=NC > - otherwise -> PBMT=Normal (PBMT=0) > > Clear the PBMT field before applying the selected encoding, and only > touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised. > > Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> > --- > drivers/iommu/generic_pt/fmt/riscv.h | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h > index a7fef6266a36..02051bb3c6e5 100644 > --- a/drivers/iommu/generic_pt/fmt/riscv.h > +++ b/drivers/iommu/generic_pt/fmt/riscv.h > @@ -58,6 +58,8 @@ enum { > RISCVPT_G = BIT(5), > RISCVPT_A = BIT(6), > RISCVPT_D = BIT(7), > + RISCVPT_NC = BIT(61), > + RISCVPT_IO = BIT(62), > RISCVPT_RSW = GENMASK(9, 8), > RISCVPT_PPN32 = GENMASK(31, 10), > > @@ -237,6 +239,13 @@ static inline int riscvpt_iommu_set_prot(struct pt_common *common, > pte |= RISCVPT_R; > if (!(iommu_prot & IOMMU_NOEXEC)) > pte |= RISCVPT_X; > + if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) { > + pte &= ~RISCVPT_PBMT; > + if (iommu_prot & IOMMU_MMIO) > + pte |= RISCVPT_IO; > + else if (!(iommu_prot & IOMMU_CACHE)) > + pte |= RISCVPT_NC; > + } > > /* Caller must specify a supported combination of flags */ > if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) == 0)) > -- > 2.50.1 > I'm okay with the current way of MMIO & CACHE mapping to IO & NC. Reviewed-by: Guo Ren <guoren@kernel.org> -- Best Regards Guo Ren _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2026-04-12 14:08 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-04-11 2:22 [PATCH 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt fangyu.yu 2026-04-11 2:22 ` [PATCH 1/2] iommu/riscv: Advertise Svpbmt support to generic page table fangyu.yu 2026-04-11 12:47 ` Jason Gunthorpe 2026-04-11 16:51 ` Anup Patel 2026-04-12 13:03 ` Guo Ren 2026-04-11 2:22 ` [PATCH 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits fangyu.yu 2026-04-11 12:47 ` Jason Gunthorpe 2026-04-11 16:51 ` Anup Patel 2026-04-12 14:08 ` Guo Ren
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox