From: fangyu.yu@linux.alibaba.com
To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca,
kevin.tian@intel.com, baolu.lu@linux.intel.com,
vasant.hegde@amd.com, anup@brainfault.org, nutty.liu@hotmail.com,
jgg@nvidia.com
Cc: guoren@kernel.org, iommu@lists.linux.dev,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Fangyu Yu <fangyu.yu@linux.alibaba.com>
Subject: [PATCH v2 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
Date: Tue, 14 Apr 2026 19:02:12 +0800 [thread overview]
Message-ID: <20260414110212.79526-3-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20260414110212.79526-1-fangyu.yu@linux.alibaba.com>
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
When the RISC-V IOMMU page table format support Svpbmt, PBMT provides
a way to tag mappings with page-based memory types. Encode memory type
via PBMT in RISC-V IOMMU PTEs:
- IOMMU_MMIO -> PBMT=IO
- !IOMMU_MMIO && !IOMMU_CACHE -> PBMT=NC
- otherwise -> PBMT=Normal (PBMT=0)
Only touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
---
drivers/iommu/generic_pt/fmt/riscv.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h
index a7fef6266a36..57e51e5def9f 100644
--- a/drivers/iommu/generic_pt/fmt/riscv.h
+++ b/drivers/iommu/generic_pt/fmt/riscv.h
@@ -64,6 +64,8 @@ enum {
RISCVPT_PPN64 = GENMASK_ULL(53, 10),
RISCVPT_PPN64_64K = GENMASK_ULL(53, 14),
RISCVPT_PBMT = GENMASK_ULL(62, 61),
+ RISCVPT_NC = BIT(61),
+ RISCVPT_IO = BIT(62),
RISCVPT_N = BIT_ULL(63),
/* Svnapot encodings for ppn[0] */
@@ -237,6 +239,12 @@ static inline int riscvpt_iommu_set_prot(struct pt_common *common,
pte |= RISCVPT_R;
if (!(iommu_prot & IOMMU_NOEXEC))
pte |= RISCVPT_X;
+ if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) {
+ if (iommu_prot & IOMMU_MMIO)
+ pte |= RISCVPT_IO;
+ else if (!(iommu_prot & IOMMU_CACHE))
+ pte |= RISCVPT_NC;
+ }
/* Caller must specify a supported combination of flags */
if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) == 0))
--
2.50.1
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next prev parent reply other threads:[~2026-04-14 11:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-14 11:02 [PATCH v2 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt fangyu.yu
2026-04-14 11:02 ` [PATCH v2 1/2] iommu/riscv: Advertise Svpbmt support to generic page table fangyu.yu
2026-04-14 11:02 ` fangyu.yu [this message]
2026-04-15 6:52 ` [PATCH v2 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits Tian, Kevin
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